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參數(shù)資料
| 型號： | P80C32-24 |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER |
| 中文描述： | 8-BIT, 24 MHz, MICROCONTROLLER, PDIP40 |
| 封裝： | PLASTIC, DIP-40 |
| 文件頁數(shù)： | 9/23頁 |
| 文件大?。?/td> | 319K |
| 代理商： | P80C32-24 |
8XC52/54/58
DC CHARACTERISTICS
(Over Operating Conditions) (Continued)
All parameter values apply to all devices unless otherwise indicated.
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
(Note 4)
V
OH1
Output High Voltage
(Port 0 in External Bus Mode)
V
CC
b
0.3
V
CC
b
0.7
V
CC
b
1.5
V
I
OH
e b
200
m
A
I
OH
e b
3.2 mA
I
OH
e b
7.0 mA
V
V
I
IL
Logical 0 Input Current
(Ports 1, 2 and 3)
b
50
m
A
V
IN
e
0.45V
V
IN
e
V
IL
or V
IH
I
LI
Input leakage Current (Port 0)
g
10
m
A
I
TL
Logical 1 to 0 Transition Current
(Ports 1, 2 and 3)
Commercial
Express
b
650
b
750
m
A
m
A
V
IN
e
2V
RRST
RST Pulldown Resistor
40
225
K
X
CIO
Pin Capacitance
10
pF
@
1 MHz, 25
§
C
I
CC
Power Supply Current:
Active Mode
at 12 MHz (Figure 5)
at 16 MHz
at 24 MHz
at 33 MHz (8XC5X-33)
Idle Mode
at 12 MHz (Figure 5)
at 16 MHz
at 24 MHz
at 33 MHz (8XC5X-33)
Power Down Mode
8XC5X-33
(Note 3)
15
20
28
35
30
38
56
56
mA
mA
mA
mA
5
6
7
7
5
5
7.5
9.5
13.5
15
75
50
mA
mA
mA
mA
m
A
m
A
NOTES:
1. Capacitive loading on Ports 0 and 2 may cause noise pulses above 0.4V to be superimposed on the V
OL
s of ALE and
Ports 1, 2 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins
change from 1 to 0. In applications where capacitive loading exceeds 100 pF, the noise pulses on these signals may exceed
0.8V. It may be desirable to qualify ALE or other signals with a Schmitt Triggers, or CMOS-level input logic.
2. Capacitive loading on Ports 0 and 2 cause the V
OH
on ALE and PSEN to drop below the 0.9 V
CC
specification when the
address lines are stabilizing.
3. See Figures 6–9 for test conditions. Minimum V
CC
for Power Down is 2V.
4. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature
and 5V.
5. Under steady state (non-transient) conditions, I
OL
must be externally limited as follows:
Maximum I
OL
per port pin:
10mA
Maximum I
OL
per 8-bit portD
Port 0:
26 mA
Ports 1, 2 and 3:
15 mA
Maximum total I
OL
for all output pins:
71 mA
If I
OL
exceeds the test condition, V
OL
may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test conditions.
9
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