參數(shù)資料
型號(hào)： P75N02LS
廠商： Electronic Theatre Controls, Inc.
英文描述： N-Channel Logic Level Enhancement Mode Field Effect Transistor
中文描述： N溝道增強(qiáng)模式的邏輯電平場(chǎng)效應(yīng)晶體管
文件頁數(shù)： 2/3頁
文件大?。?/td> 45K
代理商： P75N02LS
2
AUG-02-2001
N-Channel Logic Level Enhancement
Mode Field Effect Transistor
P75N02LS
TO-263 (D
2
PAK)
NIKO-SEM
On-State Drain Current
1
I
D(ON)
V
DS
= 10V, V
GS
= 10V
70
A
V
GS
= 10V, I
D
= 30A
5
7
Drain-Source On-State
Resistance
R
DS(ON)
V
GS
= 7V, I
D
= 24A
6
8
m
Ω
Forward Transconductance
1
g
fs
V
DS
= 15V, I
D
= 30A
16
S
DYNAMIC
Input Capacitance
C
iss
5000
Output Capacitance
C
oss
1800
Reverse Transfer Capacitance
Total Gate Charge
2
Gate-Source Charge
2
Gate-Drain Charge
2
Turn-On Delay Time
2
Rise Time
2
C
rss
V
GS
= 0V, V
DS
= 15V, f = 1MHz
800
pF
Q
g
140
Q
gs
40
Q
gd
V
DS
= 0.5V
(BR)DSS
, V
GS
= 10V,
I
D
= 35A
75
nC
t
d(on)
7
t
r
V
DS
= 15V, R
L
= 1
Ω
7
Turn-Off Delay Time
2
t
d(off)
I
D
30A, V
GS
= 10V, R
GS
= 2.5
Ω
24
Fall Time
2
t
f
6
nS
SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS (T
C
= 25 °C)
Continuous Current
Pulsed Current
3
Forward Voltage
1
I
S
75
I
SM
170
A
V
SD
I
F
= I
S
, V
GS
= 0V
1.3
V
Reverse Recovery Time
t
rr
37
nS
Peak Reverse Recovery Current
I
RM(REC)
I
F
= I
S
, dl
F
/dt = 100A /
μ
S
200
A
Reverse Recovery Charge
Q
rr
0.043
μ
C
1
Pulse test : Pulse Width
≤
300
μ
sec, Duty Cycle
≤
2
％
.
2
Independent of operating temperature.
3
Pulse width limited by maximum junction temperature.
REMARK: THE PRODUCT MARKED WITH “P75N02LS”, DATE CODE or LOT #
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