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P4C1281/P4C1282 - ULTRA HIGH SPEED 64K x 4 CMOS STATIC RAMS
Page 4
Document # SRAM136 REV OR
notes:
1. Stresses greater than those listed under MAxIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAxIMUM rating conditions for extended
periods may affect reliability.
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with V
IL and IIL not more negative than –3.0V and
–100mA, respectively, are permissible for pulse widths up to 20ns.
4. This parameter is sampled and not 100% tested.
5. WE is HIGH for READ cycle.
6. CE is LOW for READ cycle.
7. ADDRESS must be valid prior to, or coincident with CE transition
LOW.
8. Read Cycle Time is measured from the last valid address to the first
transitioning address.
9. Transition is measured ± 200 mV from steady state voltage prior to
change,withloadingasspecifiedinFigure1. Thisparameterissampled
and not 100% tested.
AC CHARACTERISTICS—WRITE CYCLE
(V
CC = 5V ± 10%, All Temperature Ranges)
(2)
Sym Parameter
-12
-15
-20
-25
-35
-45
Unit
Min Max Min Max Min Max Min Max Min Max Min Max
t
WC
Write Cycle Time
12
13
15
20
30
40
ns
t
CW
Chip Enable Time to End of Write
8
10
15
20
30
35
ns
t
AW
Address Valid to End of Write
8
10
15
20
25
35
ns
t
AS
Address Setup Time
0
ns
t
WP
Write Pulse Width
9
10
15
20
25
35
ns
t
AH
Address Hold Time from End of
Write
0
ns
t
DW
Data Valid to End of Write
6
7
10
13
15
20
ns
t
DH
Data Hold Time
0
ns
t
WZ
Write Enable to Output in High Z
6
7
8
10
15
ns
t
OW
Output Active from End of Write
2
ns
t
AWE
Write Enable to Data-out Valid
(P4C1281)
12
13
18
20
30
35
ns
t
ADV
Data-in Valid to Data-out Valid
(P4C1281)
12
13
18
20
30
35
ns