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參數(shù)資料
| 型號(hào)： | P3PSL450AHG-08CR |
| 廠商： | ON Semiconductor |
| 文件頁(yè)數(shù)： | 8/9頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK GEN EMI MODULATOR 8-WDFN |
| 標(biāo)準(zhǔn)包裝： | 3,000 |
| 系列： | Timing-Safe™ |
| 類型： | * |
| PLL： | 是 |
| 輸入： | LVCMOS |
| 輸出： | 時(shí)鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 60MHz |
| 除法器/乘法器： | 無/是 |
| 電源電壓： | 1.6 V ~ 2 V |
| 工作溫度： | -20°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-WFDFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 8-WDFN（2x2） |
| 包裝： | 帶卷 (TR) |
P3PSL450A
http://onsemi.com
8
PCB LAYOUT RECOMMENDATION
For optimum device performance, following guidelines are recommended.
Dedicated VDD and GND planes.
The device must be isolated from system power supply noise. A 0.1 mF and a 2.2 mF decoupling capacitor should be
mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between the
decoupling capacitor and VDD pin. The PCB trace to VDD pin and the ground via should be kept as short as possible.
All the VDD pins should have decoupling capacitors.
In an optimum layout all components are on the same side of the board, minimizing vias through other signal layers.
A typical layout is shown in the Figure below:
As short as
possible
As short as
possible
CLKIN
FS
PD#
GND
VDD
SSEXTR
MR
ModOUT
R
Rs
ORDERING INFORMATION
Ordering Code
Marking
Temperature
Package Type
Shipping
P3PSL450AG08CR
FA
20°C to +85°C
8 pin (2 mm x 2 mm) WDFN
(PbFree)
Tape & Reel
P3PSL450AHG08CR
FC
20°C to +85°C
8 pin (2 mm x 2 mm) WDFN
(PbFree)
Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*A “microdot” placed at the end of last row of marking or just below the last row toward the center of package indicates PbFree.
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