參數(shù)資料
型號(hào): P2V28S40ATP-75
廠商: Vanguard International Semiconductor Corporation
英文描述: 128Mb SDRAM Specification
中文描述: 128Mb的SDRAM內(nèi)存規(guī)格
文件頁數(shù): 30/51頁
文件大?。?/td> 652K
代理商: P2V28S40ATP-75
JULY.2000
Rev.2.2
128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT)
P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT)
P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
Page-29
CLK SUSPEND
CKE controls the internal CLK at the following cycle. Figure
below shows how CKE works. By negating CKE, the next
internal CLK is suspended. The purpose of CLK suspend is
power down, output suspend or input suspend. CKE is a
synchronous input except during the self-refresh mode. CLK
suspend can be performed either when the banks are active
or idle. A command at the suspended cycle is ignored.
CLK
Command
CKE
Command
CKE
Standby Power Down
Active Power Down
PRE
NOP
NOP
NOP
NOP
NOP
NOP
ACT
CLK
Command
DQ
CKE
Write
Read
D0
D1
D2
D3
Q0
Q1
Q2
Q3
ext.CLK
CKE
int.CLK
tIH
tIS
tIH
tIS
Power Down by CKE
DQ Suspend by CKE (CL=2)
相關(guān)PDF資料
PDF描述
P2V28S40ATP-8 128Mb SDRAM Specification
P2V28S20ATP-75 128Mb SDRAM Specification
P2V28S20ATP-8 128Mb SDRAM Specification
P2V28S20DTP-7 128Mb SDRAM Specification
P2V28S30ATP-7 128Mb SDRAM Specification
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