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參數(shù)資料
| 型號： | P2V28S30ATP-75 |
| 廠商： | Vanguard International Semiconductor Corporation |
| 英文描述： | 128Mb SDRAM Specification |
| 中文描述： | 128Mb的SDRAM內存規(guī)格 |
| 文件頁數(shù)： | 18/51頁 |
| 文件大小： | 652K |
| 代理商： | P2V28S30ATP-75 |
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JULY.2000
Rev.2.2
128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT)
P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT)
P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
Page-17
OPERATIONAL DESCRIPTION
BANK ACTIVATE
The SDRAM has four independent banks. Each bank is activated by
the ACT command with the bank addresses (BA0,1). A row is indi-
cated by the row addresses A0-11. The minimum activation interval
between one bank and the other bank is tRRD. Maximum 2 ACT
commands are allowed within tRC , although the number of banks
which are active concurrently is not limited.
PRECHARGE
The PRE command deactivates the bank indicated by BA0,1. When
multiple banks are active, the precharge all command (PREA, PRE
+ A10=H) is available to deactivate them at the same time.
After tRP from the precharge, an ACT command to the same bank
can be issued.
READ
After tRCD from the bank activation, a READ command can be
issued. 1st output data is available after the /CAS Latency from the
READ, followed by (BL -1) consecutive data when the Burst Length
is BL. The start address is specified by A0-A9(x4), A0-8(X8), A0-7
(X16) , and the address sequence of burst data is defined by the
Burst Type. A READ command may be applied to any active bank,
so the row precharge time (tRP) can be hidden behind continuous
output data by interleaving the multiple banks. When A10 is high at
a READ command, the auto-precharge (READA) is performed. Any
command (READ, WRITE, PRE, TBST, ACT) to the same bank is
inhibited till the internal precharge is complete. The internal precharge
starts at BL after READA. (Need to keep tRAS min.) The next ACT
command can be issued after (BL + tRP) from the previous READA.
Bank Activation and Precharge All (BL=4, CL=3)
Command
CLK
A0-9
A10
BA0,1
DQ
ACT
Xa
Xa
00
READ
Y
0
00
Qa0
Qa1
Qa2
Qa3
ACT
Xb
Xb
01
PRE
tRRD
tRCD
1
ACT
Xb
Xb
01
Precharge all
tRAS
tRP
tRCmin
2 ACT command / tRCmin
A11
Xa
Xb
Xb
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