Fusion Family of Mixed Signal FPGAs
Revision 4
2-187
Table 2-114 2.5 V LVCMOS Low Slew
Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCI = 2.3 V
Applicable to Advanced I/Os
Drive
Strength
Speed
Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
4 mA
Std.
0.66
11.40
0.04
1.31
0.43
11.22
11.40
2.68
2.20
13.45 13.63
ns
–1
0.56
9.69
0.04
1.11
0.36
9.54
9.69
2.28
1.88
11.44
11.60
ns
–2
0.49
8.51
0.03
0.98
0.32
8.38
8.51
2.00
1.65
10.05 10.18
ns
8 mA
Std.
0.66
7.96
0.04
1.31
0.43
8.11
7.81
3.05
2.89
10.34 10.05
ns
–1
0.56
6.77
0.04
1.11
0.36
6.90
6.65
2.59
2.46
8.80
8.55
ns
–2
0.49
5.94
0.03
0.98
0.32
6.05
5.84
2.28
2.16
7.72
7.50
ns
12 mA
Std.
0.66
6.18
0.04
1.31
0.43
6.29
5.92
3.30
3.32
8.53
8.15
ns
–1
0.56
5.26
0.04
1.11
0.36
5.35
5.03
2.81
2.83
7.26
6.94
ns
–2
0.49
4.61
0.03
0.98
0.32
4.70
4.42
2.47
2.48
6.37
6.09
ns
16 mA
Std.
0.66
6.18
0.04
1.31
0.43
6.29
5.92
3.30
3.32
8.53
8.15
ns
–1
0.56
5.26
0.04
1.11
0.36
5.35
5.03
2.81
2.83
7.26
6.94
ns
–2
0.49
4.61
0.03
0.98
0.32
4.70
4.42
2.47
2.48
6.37
6.09
ns
24 mA
Std.
0.66
6.18
0.04
1.31
0.43
6.29
5.92
3.30
3.32
8.53
8.15
ns
–1
0.56
5.26
0.04
1.11
0.36
5.35
5.03
2.81
2.83
7.26
6.94
ns
–2
0.49
4.61
0.03
0.98
0.32
4.70
4.42
2.47
2.48
6.37
6.09
ns
Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on