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參數(shù)資料
| 型號： | P1145-3SN-FREQ-30-OUT21 |
| 廠商： | PLETRONICS INC |
| 元件分類： | XO, clock |
| 英文描述： | CRYSTAL OSCILLATOR, CLOCK, 0.65 MHz - 69.999 MHz, CMOS OUTPUT |
| 封裝： | FULL SIZE, METAL, DIP-4 |
| 文件頁數(shù)： | 1/1頁 |
| 文件大?。?/td> | 42K |
| 代理商： | P1145-3SN-FREQ-30-OUT21 |
P1145-3S Series
Full Size (14 Pin DIP) Metal Clock Oscillator
CMOS with Enable/ Disable
Lower Ringing Noise Option Available to Reduce EMI
Available in Thru-Hole or Surface Mount Configuration
650 kHz – 69.999 MHz
Standard Specifications
Overall Frequency Stability
P1145-3S: ± 50 PPM, P1144-3S: ± 25 PPM, P1120-3S: ± 20 PPM over Operating Temp. Range
Operating Temperature Range
0 to +70°C is standard, but can be extended to- 40 to +85°C for certain frequencies
Supply Voltage (Vcc)
5.0 volts and 3.3 volts available
Symmetry (Duty Cycle)
40/60 to 60/40% is standard, but 45/55% at 50% of Vcc is also available (see Waveform 1)
Output Load
Enable/Disable Option (E/D)
Output enabled when Pin #1 is open or at Logic “1”; Output disabled when Pin #1 is at Logic “0”.
Supply Current
Rise and Fall Time
Frequency Range
(MHz)
Typical
Maximum
Typical
Maximum
0.650 – 10.000
6.5
10.0
3.0
4.0
10.001 – 25.999
15.0
20.0
2.5
3.5
26.000 – 34.999
18.0
25.0
2.5
3.5
35.000 – 50.000
25.0
30.0
2.5
3.5
Part Numbering Guide
Model
Frequency Stability
45 = ± 50 PPM
44 = ± 25 PPM
Frequency in MHz
Special Specifications (choose all that apply)
P11 45 - 3S
V -- 60.0M - 30 - SMD
Consult factory for available frequencies and specs. Not all options available for all frequencies. A special part number may be assigned.
Blank: Std Specs (5.0V ± 10%, 0 to +70 C, 40/60% Sym)
E: Extended Operating Temperature Range (- 40 to +85 C)
N: Lower Ringing Noise
S: 45/55% Symmetry at 50% of Vcc
V: Supply Voltage of 3.3 volts
°
19013 36th Ave. West Suite H Lynnwood, WA 98036, USA
± 10%
50.001 – 69.999
32.0
35.0
2.5
3.5
Frequency Stability is inclusive of frequency shifts due to calibration, temperature, supply voltage, shock, vibration and load
Surface Mount Option
Mechanical:
not to scale
inches (mm)
Surface Mount
(425) 776 -1880, Fax: (425) 776-2760, ple-sales@pletronics.com, www.pletronics.com
17
Jan 2002
Solder pad layout may use any combination of pins 1, 7, 8 & 14 shown.
Recommended pad size is .12 (3.1) x .07 (1.8) typical.
Pl tronics, Inc.
.807 (20.5) MAX
PLETRONICS
.500
(12.7)
MAX
.247 (6.28)
MAX
.200 (5.08)
MAX
.600 (15.24)
.300
(7.62)
1
7
14
8
E/D
Vcc
OUT
GND
.031 (0.8)
.560
(14.23)
MAX
.300
(7.62)
.200 (5.08) TYP
1
14
8 8
8
7
.250 (6.35) MAX
.020
(.51)
.820 (20.84) MAX
.767 (19.49)
.600 (15.24)
Standard load is 15pF maximum, see Test Circuit 3 (consult factory for heavier loads)
Icc (mA) w/ 15pF load
Tr & Tf (nS) w/ 15pF load
Packaging
Tube or on Pads,
SMD: Bulk
Due to part size and factory abilities, part marking may vary from lot to lot and may contain our part number or an internal code.
Non-Std Output Load: Blank = 15 pF max,
30 = 30 pF max,
50 = 50 pF max
Logic Levels
Logic “1” 90% of Vcc MIN; Logic “0” 10% of Vcc MAX
20 = ± 20 PPM
Ringing Noise
Depends on frequency and output load. See EMI application note
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