參數(shù)資料
型號： ORSO82G5-1FN680I
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 101/153頁
文件大?。?/td> 0K
描述： IC TRANCEIVERS FPSC 680FPBGA
產(chǎn)品變化通告： Product Discontinuation 01/Aug/2011
標準包裝： 24
系列： *
Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
51
Figure 37. Link Header Byte
Table 10. Link Header Format
In cell mode, multiple SERDES links are used to achieve desired bandwidth. Data are cell-striped in a round-robin
fashion across two or eight links by the transmitter and then re-assembled back into a single cell stream (destrip-
ing) by the receiver. This is shown in Figure 38.
Figure 38. Multi-Link Interface - Two-Link Example
To assist with cell delineation, each link transmitter assigns sequence numbers to cells (LSEQN[6:0] bits in the Link
Header byte) before sending them out on the link. Each link increments its sequence numbers independently as
shown in Figure 38. All links reset their sequence number generator at the beginning of a SONET frame (All links
are synchronized to the start of a frame).
On the receiving side, each receiver uses the sequence numbers to verify the correct cell delineation. Since the
links were synchronized to the start of the SONET frame, all links will have cells with the same sequence number
available at the same time (although deskew needs to happen to properly align the cells). This allows the receiver
to correctly reconstruct the original cell stream.
If an unexpected sequence number is received, the receiver does not use the received value as the basis for the
next expected sequence number. Rather the old expected value is incremented by one, forming the new expected
value. An error ag is sent to the software register interface and the cell will be marked with an error. For example,
assume that the receiver expected to receive a cell with sequence number 27, but received one with sequence
number 37. The cell will be marked with an error. The receiver then expects to receive a cell with sequence number
28.
Location
Field/Description
7
Idle: Idle Cell Indicator
0: User Cell (contains valid data)
1: Idle Cell (no data in the cell payload)
6:0
LSEQ: Link Sequence Number. This value is used when aligning cells from
multiple links when doing link group multiplexing.
LIDLE
LSEQN[6:0]
LINK HEADER BYTE
Time
TRANSMITTER
Time
3
2
1
0
7
6
5
4
CELL STRIPING
0
1
LSEQ = 3
Cell = 7
LSEQ = 2
Cell = 5
LSEQ = 1
Cell = 3
LSEQ = 0
Cell = 1
Time
RECEIVER
3
2
1
0
7
6
5
4
CELL DE-STRIPING
0
1
LSEQ = 3
Cell = 6
LSEQ = 2
Cell = 4
LSEQ = 1
Cell = 2
LSEQ = 0
Cell = 0
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相關代理商/技術參數(shù)
參數(shù)描述
ORSO82G5-1FN680I1 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-2BM680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-2BM680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-2F680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 2.7Gbits/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-2F680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 2.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
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