參數(shù)資料
型號(hào)： OR3T125-5BC600I
英文描述： Dual 1.8V, 1MHz OP, -40C to +125C, 8-PDIP, TUBE
中文描述： 現(xiàn)場(chǎng)可編程門陣列（FPGA）
文件頁(yè)數(shù)： 3/210頁(yè)
文件大?。?/td> 4663K
代理商： OR3T125-5BC600I
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Table of Contents
Page
Contents
Contents
Page
Lucent Technologies Inc.
3
ORCA Series 3C and 3T FPGAs
June 1999
Data Sheet
Package Coplanarity ...............................................196
Package Parasitics..................................................196
Package Outline Diagrams......................................197
Terms and Definitions ...........................................197
208-Pin SQFP .......................................................198
208-Pin SQFP2 .....................................................199
240-Pin SQFP .......................................................200
240-Pin SQFP2 .....................................................201
256-Pin PBGA .......................................................202
352-Pin PBGA .......................................................203
432-Pin EBGA .......................................................204
600-Pin EBGA .......................................................205
Ordering Information................................................206
Index........................................................................207
Tables
Table 1. ORCA Series 3 (3C and 3T) FPGAs ............2
Table 2. ORCA Series 3 System Performance ..........6
Table 3. Look-Up Table Operating Modes ...............13
Table 4. Control Input Functionality ..........................14
Table 5. Ripple Mode Equality Comparator
Functions and Outputs ............................................18
Table 6. SLIC Modes ................................................21
Table 7. Configuration RAM Controlled
Latch/Flip-Flop Operation ........................................25
Table 8. Inter-PLC Routing Resources .....................31
Table 9. PIO Options ................................................37
Table 10. PIO Logic Options ....................................43
Table 11. PIO Register Control Signals ....................43
Table 12. Readback Options ....................................54
Table 13. Boundary-Scan Instructions .....................58
Table 14. Boundary-Scan ID Code ...........................59
Table 15. TAP Controller Input/Outputs ...................61
Table 16. PowerPCMPI Configuration .....................65
Table 17. i960/MPI Configuration .............................66
Table 18. MPI Internal Interface Signals ..................67
Table 19. MPI Setup and Control Registers .............68
Table 20. MPI Setup and Control Registers
Description ...............................................................68
Table 21. MPI Control Register 2 .............................69
Table 22. Status Register .........................................70
Table 23. Device ID Code ........................................71
Table 24. Series 3 Family and Device ID Values .....71
Table 25. ORCA Series 3 Device ID Descriptions ....71
Table 26. PCM Registers .........................................73
Table 27. DLL Mode Delay/1x Duty Cycle
Programming Values ...............................................75
Table 28. DLL Mode Delay/2x Duty Cycle
Programming Values ...............................................76
Table 29. PCM Oscillator Frequency Range 3Txxx .78
Table 30. PCM Oscillator Frequency Range 3Cxx ...78
Table 31. PCM Control Registers .............................80
Table 32. Configuration Frame Format and
Contents ..................................................................90
Table 33. Configuration Frame Size .........................91
Table 34. Configuration Modes ................................92
Table 35. Absolute Maximum Ratings ....................100
Table 36. Recommended Operating Conditions ....100
Table 37. Electrical Characteristics ........................101
Table 38. Derating for Commercial Devices
(OR3Cxx) ..............................................................103
Table 39. Derating for Industrial Devices (OR3Cxx) 103
Table 40. Derating for Commercial/Industrial
Devices (OR3Txxx) ...............................................103
Table 41. Combinatorial PFU Timing
Characteristics .......................................................104
Table 42. Sequential PFU Timing Characteristics ..106
Table 43. Ripple Mode PFU Timing
Characteristics .......................................................107
Table 44. Synchronous Memory Write
Characteristics .......................................................109
Table 45. Synchronous Memory Read
Characteristics .......................................................110
Table 46. PFU Output MUX and Direct Routing
Timing Characteristics ...........................................111
Table 47. Supplemental Logic and Interconnect
Cell (SLIC) Timing Characteristics ........................111
Table 48. Programmable I/O (PIO) Timing
Characteristics .......................................................112
Table 49. Microprocessor Interface (MPI) Timing
Characteristics .......................................................115
Table 50. Programmable Clock Manager (PCM)
Timing Characteristics (Preliminary Information) ..121
Table 51. Boundary-Scan Timing Characteristics ..122
Table 52. ExpressCLK (ECLK) and Fast Clock
(FCLK) Timing Characteristics ..............................123
Table 53. General-Purpose Clock Timing
Characteristics (Internally Generated Clock) .........124
Table 54. OR3Cxx ExpressCLK to Output Delay
(Pin-to-Pin) ............................................................125
Table 55. OR3Cxx Fast Clock (FCLK) to Output
Delay (Pin-to-Pin) ..................................................126
Table 56. OR3Cxx General System Clock (SCLK)
to Output Delay (Pin-to-Pin) ..................................127
Table 57. OR3C/Txxx Input to ExpressCLK (ECLK)
Fast-Capture Setup/Hold Time (Pin-to-Pin) ..........128
Table 58. OR3C/Txxx Input to Fast Clock
Setup/Hold Time (Pin-to-Pin) ................................130
Table 59. OR3C/Txxx Input to General System
Clock (SCLK) Setup/Hold Time (Pin-to-Pin) ..........132
Table 60. General Configuration Mode Timing
Characteristics .......................................................133
Table 61. Master Serial Configuration Mode Timing
相關(guān)PDF資料
PDF描述
OR3T125-5PS208I Dual 1.8V, 1MHz OP, I temp, -40C to +85C, 8-MSOP, TUBE
OR3T125-5PS240I Dual 1.8V, 1MHz OP, I temp, -40C to +85C, 8-PDIP, TUBE
OR3T125-6BC432I Field Programmable Gate Array (FPGA)
OR3T125-6BC600I Dual 1.8V, 1MHz OP, -40C to +125C, 8-SOIC 150mil, T/R
OR3T125-6PS208I Field Programmable Gate Array (FPGA)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
OR3T125-5PS208 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays
OR3T125-5PS208I 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays
OR3T125-5PS240 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays
OR3T125-5PS240I 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays
OR3T125-6BA352 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays
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