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| 型號： | OR2T40A7BC432-DB |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 900 CLBS, 43200 GATES, PBGA432 |
| 封裝： | EBGA-432 |
| 文件頁數(shù)： | 143/196頁 |
| 文件大小： | 3475K |
| 代理商： | OR2T40A7BC432-DB |
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50
Lattice Semiconductor
Data Sheet
ORCA Series 2 FPGAs
January 2003
FPGA Conguration Modes (continued)
Master Serial Mode
In the master serial mode, the FPGA loads the congu-
ration data from an external serial ROM. The congura-
tion data is either loaded automatically at start-up or on
a PRGM command to recongure. The ATT1700 and
ATT1700A Series can be used to congure the FPGA
in the master serial mode. This provides a simple 4-pin
interface in an 8-pin package. The ATT1736, ATT1765,
and ATT17128 serial ROMs store 32K, 64K, and 128K
bits, respectively.
Conguration in the master serial mode can be done at
powerup and/or upon a congure command. The sys-
tem or the FPGA must activate the serial ROM's
RESET
/OE and CE inputs. At powerup, the FPGA and
serial ROM each contain internal power-on reset cir-
cuitry that allows the FPGA to be congured without
the system providing an external signal. The power-on
reset circuitry causes the serial ROM's internal address
pointer to be reset. After powerup, the FPGA automati-
cally enters its initialization phase.
The serial ROM/FPGA interface used depends on such
factors as the availability of a system reset pulse, avail-
ability of an intelligent host to generate a congure
command, whether a single serial ROM is used or mul-
tiple serial ROMs are cascaded, whether the serial
ROM contains a single or multiple conguration pro-
grams, etc. Because of differing system requirements
and capabilities, a single FPGA/serial ROM interface is
generally not appropriate for all applications.
Data is read in the FPGA sequentially from the serial
ROM. The DATA output from the serial ROM is con-
nected directly into the DIN input of the FPGA. The
CCLK output from the FPGA is connected to the
CLOCK input of the serial ROM. During the congura-
tion process, CCLK clocks one data bit on each rising
edge.
Since the data and clock are direct connects, the
FPGA/serial ROM design task is to use the system or
FPGA to enable the RESET/OE and CE of the serial
ROM(s). There are several methods for enabling the
serial ROM’s RESET/OE and CE inputs. The serial
ROM's RESET/OE is programmable to function with
RESET active-high and OE active-low or RESET active-
low and OE active-high.
In Figure 41, serial ROMs are cascaded to congure
multiple daisy-chained FPGAs. The host generates a
500 ns low pulse into the FPGA's PRGM input. The
FPGA’s INIT input is connected to the serial ROM’s
RESET
/OE input, which has been programmed to
function with RESET active-low and OE active-high.
The FPGA DONE is routed to the CE pin. The low on
DONE enables the serial ROMs. At the completion of
conguration, the high on the FPGA's DONE disables
the serial ROM.
Serial ROMs can also be cascaded to support the con-
guration of multiple FPGAs or to load a single FPGA
when conguration data requirements exceed the
capacity of a single serial ROM. After the last bit from
the rst serial ROM is read, the serial ROM outputs
CEO
low and 3-states the DATA output. The next serial
ROM recognizes the low on CE input and outputs con-
guration data on the DATA output. After conguration
is complete, the FPGA’s DONE output into CE disables
the serial ROMs.
This FPGA/serial ROM interface is not used in applica-
tions in which a serial ROM stores multiple congura-
tion programs. In these applications, the next
conguration program to be loaded is stored at the
ROM location that follows the last address for the previ-
ous conguration program. The reason the interface in
Figure 41 will not work in this application is that the low
output on the INIT signal would reset the serial ROM
address pointer, causing the rst conguration to be
reloaded.
In some applications, there can be contention on the
FPGA's DIN pin. During conguration, DIN receives
conguration data, and after conguration, it is a user
I/O. If there is contention, an early DONE at start-up
(selected in ORCA Foundry) may correct the problem.
An alternative is to use LDC to drive the serial ROM's
CE
pin. In order to reduce noise, it is generally better to
run the master serial conguration at 1.25 MHz (M3 pin
tied high), rather than 10 MHz, if possible.
Figure 41. Master Serial Conguration Schematic
ATT1700A
DIN
M2
M1
M0
ORCA
SERIES
FPGA
CCLK
DOUT
TO DAISY-
CHAINED
DEVICES
DATA
CLK
CE
CEO
ATT1700A
DATA
CLK
RESET/OE
CEO
CE
TO MORE
SERIAL ROMs
AS NEEDED
DONE
INIT
PROGRAM
RESET/OE
PRGM
5-4456.1(F)
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