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| 型號： | OR2T40A6BC432I-DB |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 900 CLBS, 43200 GATES, PBGA432 |
| 封裝： | EBGA-432 |
| 文件頁數(shù)： | 33/196頁 |
| 文件大小： | 3475K |
| 代理商： | OR2T40A6BC432I-DB |
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128
Lattice Semiconductor
Data Sheet
ORCA Series 2 FPGAs
January 2003
Package Thermal Characteristics
There are three thermal parameters that are in com-
mon use: ΘJA, ψJC, and ΘJC. It should be noted that all
the parameters are affected, to varying degrees, by
package design (including paddle size) and choice of
materials, the amount of copper in the test board or
system board, and system airow.
Table 29 contains the currently available thermal speci-
cations for FPGA packages mounted on both JEDEC
and non-JEDEC test boards. The thermal values for the
newer package types correspond to those packages
mounted on a JEDEC four-layer board (indicated as
Note 2 in the table). The values for the older packages,
however, correspond to those packages mounted on a
non-JEDEC, single-layer, sparse copper board (see
Note 1). It should also be noted that the values for the
older packages are considered conservative.
Θ
ΘJA
This is the thermal resistance from junction to ambient
(a.k.a. theta-JA, R-theta, etc.).
where TJ is the junction temperature, TA is the ambient
air temperature, and Q is the chip power.
Experimentally, ΘJA is determined when a special ther-
mal test die is assembled into the package of interest,
and the part is mounted on the thermal test board. The
diodes on the test chip are separately calibrated in an
oven. The package/board is placed either in a JEDEC
natural convection box or in the wind tunnel, the latter
for forced convection measurements. A controlled
amount of power (Q) is dissipated in the test chip’s
heater resistor, the chip’s temperature (TJ) is deter-
mined by the forward drop on the diodes, and the ambi-
ent temperature (TA) is noted. Note that ΘJA is
expressed in units of °C/watt.
ψ
ψJC
This JEDEC designated parameter correlates the junc-
tion temperature to the case temperature. It is generally
used to infer the junction temperature while the device
is operating in the system. It is not considered a true
thermal resistance, and it is dened by:
where TC is the case temperature at top dead center,
TJ is the junction temperature, and Q is the chip power.
During the ΘJA measurements described above,
besides the other parameters measured, an additional
temperature reading, TC, is made with a thermocouple
attached at top-dead-center of the case. ψJC is also
expressed in units of °C/watt.
ΘJC
This is the thermal resistance from junction to case. It
is most often used when attaching a heat sink to the
top of the package. It is dened by:
The parameters in this equation have been dened
above. However, the measurements is performed with
the case of the part pressed against a water-cooled
heat sink so as to draw most of the heat generated by
the chip out the top of the package. It is this difference
in the measurement process that differentiates ΘJC
from ψJC. ΘJC is a true thermal resistance and is
expressed in units of °C/watt.
ΘJB
This is the thermal resistance from junction to board
(a.k.a., ΘJL). It is dened by:
where TB is the temperature of the board adjacent to a
lead measured with a thermocouple. The other param-
eters on the right-hand side have been dened above.
This is considered a true thermal resistance, and the
measurement is made with a water-cooled heat sink
pressed against the board so as to draw most of the
heat out of the leads. Note that ΘJB is expressed in
units of °C/watt, and that this parameter and the way it
is measured is still in JEDEC committee.
ΘJA
TJ
TA
–
Q
--------------------
=
ψJC
TJ
TC
–
Q
--------------------
=
ΘJC
TJ
TC
–
Q
--------------------
=
ΘJB
TJ
TB
–
Q
--------------------
=
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| OR2T40A7BC432-DB | FPGA, 900 CLBS, 43200 GATES, PBGA432 |
| OR2C08A-2B256 | FPGA, 196 CLBS, 7000 GATES, PBGA256 |
| OR2C08A-3B256 | FPGA, 196 CLBS, 7000 GATES, PBGA256 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OR2T40A6PS208-DB | 功能描述:FPGA - 現(xiàn)場可編程門陣列 3600 LUT 326 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR2T40A6PS208I-DB | 功能描述:FPGA - 現(xiàn)場可編程門陣列 3600 LUT 326 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR2T40A6PS240DB | 制造商:ORCA 功能描述:NEW |
| OR2T40A6PS240-DB | 功能描述:FPGA - 現(xiàn)場可編程門陣列 3600 LUT 326 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR2T40A6PS240I-DB | 功能描述:FPGA - 現(xiàn)場可編程門陣列 3600 LUT 326 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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