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| 型號： | OR2T10A4S240-DB |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 256 CLBS, 12300 GATES, PQFP240 |
| 封裝： | SQFP-240 |
| 文件頁數(shù)： | 134/196頁 |
| 文件大?。?/td> | 1393K |
| 代理商： | OR2T10A4S240-DB |
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42
Lattice Semiconductor
Data Sheet
ORCA Series 2 FPGAs
November 2006
FPGA States of Operation
Prior to becoming operational, the FPGA goes through a
sequence of states, including initialization, conguration,
and start-up. Figure 36 outlines these three FPGA
states.
5-4529(F).r6
Figure 36. FPGA States of Operation
Initialization
Upon powerup, the device goes through an initialization
process. First, an internal power-on-reset circuit is trig-
gered when power is applied. When VDD reaches the
voltage at which portions of the FPGA begin to operate
(2.5 V to 3 V for the OR2CxxA, 2.2 V to 2.7 V for the
OR2TxxA/OR2TxxB), the I/Os are congured based on
the conguration mode, as determined by the mode
select inputs M[2:0]. A time-out delay is initiated when
VDD reaches between 3.0 V and 4.0 V (OR2CxxA) or
2.7 V to 3.0 V (OR2TxxA/2TxxB) to allow the power
supply voltage to stabilize. The INIT and DONE outputs
are low. At powerup, if VDD does not rise from 2.0 V to
VDD in less than 25 ms, the user should delay congu-
ration by inputting a low into INIT, PRGM, or RESET
until VDD is greater than the recommended minimum
operating voltage (4.75 V for OR2CxxA commercial
devices and 3.0 V for OR2TxxA/B devices).
At the end of initialization, the default conguration
option is that the conguration RAM is written to a low
state. This prevents shorts prior to conguration. As a
conguration option, after the rst conguration (i.e., at
reconguration), the user can recongure without
clearing the internal conguration RAM rst.
The active-low, open-drain initialization signal INIT is
released and must be pulled high by an external resis-
tor when initialization is complete. To synchronize the
conguration of multiple FPGAs, one or more INIT pins
should be wire-ANDed. If INIT is held low by one or
more FPGAs or an external device, the FPGA remains
in the initialization state. INIT can be used to signal that
the FPGAs are not yet initialized. After INIT goes high
for two internal clock cycles, the mode lines (M[3:0])
are sampled and the FPGA enters the conguration
state.
The high during conguration (HDC), low during cong-
uration (LDC), and DONE signals are active outputs in
the FPGA’s initialization and conguration states. HDC,
LDC, and DONE can be used to provide control of
external logic signals such as reset, bus enable, or
PROM enable during conguration. For parallel master
conguration modes, these signals provide PROM
enable control and allow the data pins to be shared
with user logic signals.
If conguration has begun, an assertion of RESET or
PRGM initiates an abort, returning the FPGA to the ini-
tialization state. The PRGM and RESET pins must be
pulled back high before the FPGA will enter the cong-
uration state. During the start-up and operating states,
only the assertion of PRGM causes a reconguration.
In the master conguration modes, the FPGA is the
source of conguration clock (CCLK). In this mode, the
initialization state is extended to ensure that, in daisy-
chain operation, all daisy-chained slave devices are
ready. Independent of differences in clock rates, master
mode devices remain in the initialization state an addi-
tional six internal clock cycles after INIT goes high.
When conguration is initiated, a counter in the FPGA
is set to 0 and begins to count conguration clock
cycles applied to the FPGA. As each conguration data
frame is supplied to the FPGA, it is internally assem-
bled into data words. Each data word is loaded into the
internal conguration memory. The conguration load-
ing process is complete when the internal length count
equals the loaded length count in the length count eld,
and the required end of conguration frame is written.
– ACTIVE I/O
– RELEASE INTERNAL RESET
– DONE GOES HIGH
START-UP
INITIALIZATION
CONFIGURATION
RESET
OR
PRGM
LOW
PRGM
LOW
– CLEAR CONFIGURATION MEMORY
– INIT LOW, HDC HIGH, LDC LOW
OPERATION
POWERUP
– POWER-ON TIME DELAY
– M[3:0] MODE IS SELECTED
– CONFIGURATION DATA FRAME WRITTEN
– INIT HIGH, HDC HIGH, LDC LOW
– DOUT ACTIVE
YES
NO
RESET,
INIT,
OR
PRGM
LOW
BIT
ERROR
YES
Select
devices
have
been
discontinued.
See
Ordering
Information
section
for
product
status.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| OR2T10A4S240I-DB | FPGA, 256 CLBS, 12300 GATES, PQFP240 |
| OR2T10A5BA256-DB | FPGA, 256 CLBS, 12300 GATES, PBGA256 |
| OR2T10A5BA352-DB | FPGA, 256 CLBS, 12300 GATES, PBGA352 |
| OR2T10A5M84-D | FPGA, 256 CLBS, 12300 GATES, PQCC84 |
| OR2T10A5S208-DB | FPGA, 256 CLBS, 12300 GATES, PQFP208 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OR2T10A4S240I-DB | 功能描述:FPGA - 現(xiàn)場可編程門陣列 1024 LUT 244 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR2T10A5BA256-DB | 功能描述:FPGA - 現(xiàn)場可編程門陣列 1024 LUT 244 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR2T10A5J160-DB | 功能描述:FPGA - 現(xiàn)場可編程門陣列 1024 LUT 244 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR2T10A5S208-DB | 功能描述:FPGA - 現(xiàn)場可編程門陣列 1024 LUT 244 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR2T10A5S240-DB | 功能描述:FPGA - 現(xiàn)場可編程門陣列 Use ECP/EC or XP RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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