參數(shù)資料
型號(hào)： OR2T08A-5BA240
廠商： Electronic Theatre Controls, Inc.
元件分類： FPGA
英文描述： Field-Programmable Gate Arrays
中文描述： 現(xiàn)場(chǎng)可編程門陣列
文件頁(yè)數(shù)： 116/192頁(yè)
文件大小： 3148K
代理商： OR2T08A-5BA240
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Data Sheet
June 1999
ORCA Series 2 FPGAs
Lucent Technologies Inc.
3
Description
The
ORCA Series 2 series of SRAM-based FPGAs are
an enhanced version of the ATT2C/2T architecture.
The latest
ORCA series includes patented architectural
enhancements that make functions faster and easier to
design while conserving the use of PLCs and routing
resources.
The Series 2 devices can be used as drop-in replace-
ments for the ATT2Cxx/ATT2Txx series, respectively,
other. The usable gate counts associated with each
series are provided in Table 1. Both series are offered
in a variety of packages, speed grades, and tempera-
ture ranges.
The
ORCA series FPGA consists of two basic ele-
ments: programmable logic cells (PLCs) and program-
mable input/output cells (PICs). An array of PLCs is
surrounded by PICs as shown in Figure 1. Each PLC
contains a programmable function unit (PFU). The
PLCs and PICs also contain routing resources and
configuration RAM. All logic is done in the PFU. Each
PFU contains four 16-bit look-up tables (LUTs) and four
latches/flip-flops (FFs).
The PLC architecture provides a balanced mix of logic
and routing that allows a higher utilized gate/PFU than
alternative architectures. The routing resources carry
logic signals between PFUs and I/O pads. The routing
in the PLC is symmetrical about the horizontal and ver-
tical axes. This improves routability by allowing a bus of
signals to be routed into the PLC from any direction.
Some examples of the resources required and the per-
formance that can be achieved using these devices are
represented in Table 2.
Table 2
. ORCA Series 2 System Performance
1. Implemented using 4 x 1 multiplier mode (unpipelined), register-to-register, two 8-bit inputs, one 16-bit output.
2. Implemented using two 16 x 12 ROMs and one 12-bit adder, one 8-bit input, one fixed operand, one 16-bit output.
3. Implemented using 4 x 1 multiplier mode (fully pipelined), two 8-bit inputs, one 16-bit output (28 of 44 PFUs contain only pipelining registers).
4. Implemented using 16 x 4 synchronous single-port RAM mode allowing both read and write per clock cycle, including write/read address
multiplexer.
5. Implemented using 16 x 4 synchronous single-port RAM mode allowing either read or write per clock cycle, including write/read address mul-
tiplexer.
6. Implemented using 16 x 2 synchronous dual-port RAM mode.
7. OR2TxxB available only in -7 and -8 speeds only.
8. Speed grades of -5, -6, and -7 are for OR2TxxA devices only.
Function
#
PFUs
Speed Grade
Unit
-2A
-3A
-4A
-5A
-6A
-7A
-7B
-8B
16-bit loadable up/down
counter
4
51.0
66.7
87.0
104.2
129.9
144.9
131.6
149.3
MHz
16-bit accumulator
4
51.0
66.7
87.0
104.2
129.9
144.9
131.6
149.3
MHz
8 x 8 parallel multiplier:
— Multiplier mode, unpipelined1
— ROM mode, unpipelined2
— Multiplier mode, pipelined3
22
9
44
14.2
41.5
50.5
19.3
55.6
69.0
25.1
71.9
82.0
31.0
87.7
103.1
36.0
107.5
125.0
40.3
122.0
142.9
37.7
103.1
123.5
44.8
120.5
142.9
MHz
32 x 16 RAM:
— Single port (read and write/
cycle)4
— Single port5
— Dual port6
9
16
21.8
38.2
28.6
52.6
36.2
69.0
83.3
53.8
92.6
53.8
92.6
62.5
96.2
57.5
97.7
69.4
112.4
MHz
36-bit parity check (internal)
4
13.9
11.0
9.1
7.4
5.6
5.2
6.1
5.1
ns
32-bit address decode
(internal)
3.25
12.3
9.5
7.5
6.1
4.6
4.3
4.8
4.0
ns
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OR2T08A5BA256-DB 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 Use ECP/EC or XP RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
OR2T08A5J160-DB 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 784 LUT 209 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
OR2T08A5M84-D 制造商:Lattice Semiconductor Corporation 功能描述:
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OR2T08A5S240-DB 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 784 LUT 209 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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