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| 型號(hào)： | OR2C26A3BA352I-DB |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類(lèi)： | FPGA |
| 英文描述： | FPGA, 576 CLBS, 27600 GATES, PBGA352 |
| 封裝： | PLASTIC, BGA-352 |
| 文件頁(yè)數(shù)： | 162/196頁(yè) |
| 文件大小： | 3475K |
| 代理商： | OR2C26A3BA352I-DB |
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Data Sheet
ORCA Series 2 FPGAs
January 2003
68
Lattice Semiconductor
Pin Information
Pin Descriptions
This section describes the pins found on the Series 2 FPGAs. Any pin not described in this table is a user-program-
mable I/O. During conguration, the user-programmable I/Os are 3-stated with an internal pull-up resistor enabled.
Table 17. Pin Descriptions
Symbol
I/O
Description
Dedicated Pins
VDD
—Positive power supply.
GND
—
Ground supply.
I/O-VDD5—
5 V tolerant select. (For 2TxxA only.) All VDD5 pins must be tied to either the 5 V power
supply if 5 V tolerant I/O buffers are to be used, or to the 3.3 V power supply (VDD) if
they are not. For 2CxxA and 2TxxB devices, these pins are user-programmable I/Os.
RESET
I
During conguration, RESET forces the restart of conguration and a pull-up is
enabled. After conguration, RESET can be used as a general FPGA input or as a
direct input, which causes all PLC latches/FFs to be asynchronously set/reset.
CCLK
I
In the master and asynchronous peripheral modes, CCLK is an output which strobes
conguration data in. In the slave or synchronous peripheral mode, CCLK is input syn-
chronous with the data on DIN or D[7:0].
DONE
I/O
DONE is a bidirectional pin with an optional pull-up resistor. As an active-high, open-
drain output, a high-level on this signal indicates that conguration is complete. As an
input, a low level on DONE delays FPGA start-up after conguration*.
PRGM
I
PRGM is an active-low input that forces the restart of conguration and resets the
boundary-scan circuitry. This pin always has an active pull-up.
RD_CFG
I
This pin must be held high during device initialization until the INIT pin goes high.
This pin always has an active pullup.
During conguration, RD_CFG is an active-low input that activates the TS_ALL function
and 3-states all of the I/O.
After conguration, RD_CFG can be selected (via a bit stream option) to activate the
TS_ALL function as described above, or, if readback is enabled via a bit stream option,
a high-to-low transition on RD_CFG will initiate readback of the conguration data,
including PFU output states, starting with frame address 0.
RD_DATA/TDO
O
RD_DATA/TDO is a dual-function pin. If used for readback, RD_DATA provides congu-
ration data out. If used in boundary scan, TDO is test data out.
Special-Purpose Pins (Become User I/O After Conguration)
RDY/RCLK
O
During conguration in peripheral mode, RDY indicates another byte can be written to
the FPGA. If a read operation is done when the device is selected, the same status is
also available on D7 in asynchronous peripheral mode. After conguration, the pin is a
user-programmable I/O*.
During the master parallel conguration mode RCLK, which is a read output signal to an
external memory. This output is not normally used. After conguration, this pin is a user-
programmable I/O pin*.
DIN
I
During slave serial or master serial conguration modes, DIN accepts serial congura-
tion data synchronous with CCLK. During parallel conguration modes, DIN is the D0
input. During conguration, a pull-up is enabled, and after conguration, this pin is a
user-programmable I/O pin*.
* The FPGA States of Operation section contains more information on how to control these signals during start-up. The timing of DONE
release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other conguration pins (and the acti-
vation of all user I/Os) is controlled by a second set of options.
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PDF描述 |
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| OR2C26A4BA352-DB | FPGA, 576 CLBS, 27600 GATES, PBGA352 |
| OR2C26A4BC432-DB | FPGA, 576 CLBS, 27600 GATES, PBGA432 |
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| OR2T10A4BA352I-DB | FPGA, 256 CLBS, 12300 GATES, PBGA352 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OR2C26A3PS208I-DB | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 2304 LUT 342 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR2C26A3PS208-N-DB | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Lattice Semiconductor Corporation 功能描述: |
| OR2C26A3PS240I-DB | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 2304 LUT 342 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR2C26A3PS304I-DB | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 Use ECP/EC or XP RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR2C26A-4BA352 | 制造商:ORCA 功能描述: |
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