- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383694 > OPA847 Wideband, Ultra-Low Noise, Voltage-Feedback PDF資料下載
參數(shù)資料
| 型號： | OPA847 |
| 英文描述： | Wideband, Ultra-Low Noise, Voltage-Feedback |
| 中文描述： | 寬帶，超低噪聲，電壓反饋 |
| 文件頁數(shù)： | 19/23頁 |
| 文件大小： | 529K |
| 代理商： | OPA847 |
OPA847
SBOS251C
19
www.ti.com
The shutdown feature for the OPA847 is a positive-supply
referenced, current-controlled interface. Open-collector (or
drain) interfaces are most effective, as long as the controlling
logic can sustain the resulting voltage (in open mode) that
appears at the V
DIS
pin. The V
DIS
pin voltage is one diode
below the positive supply voltage applied to the OPA847 if the
logic voltage is open. For voltage output logic interfaces, the
on/off voltage levels described in the Electrical Characteristics
apply only for a +5V supply. An open-drain interface is
recommended for a shutdown operation using a higher
positive supply and/or logic families with inadequate high-
level voltage swings.
THERMAL ANALYSIS
The OPA847 does not require heatsinking or airflow in most
applications. Maximum desired junction temperature sets the
maximum allowed internal power dissipation, as described
here. In no case should the maximum junction temperature
be allowed to exceed 150°C.
Operating junction temperature (T
J
) is given by T
A
+ P
D
θ
JA
.
The total internal power dissipation (P
D
) is the sum of
quiescent power (P
DQ
) and additional power dissipated in the
output stage (P
DL
) to deliver load power. Quiescent power is
simply the specified no-load supply current times the total
supply voltage across the part. P
DL
depends on the required
output signal and load but would, for a grounded resistive
load, be at a maximum when the output is fixed at a voltage
equal to half either supply voltage (for equal bipolar sup-
plies). Under this worst-case condition, P
DL
= V
S2
/(4 R
L
),
where R
L
includes feedback network loading. This is the
absolute highest power that can be dissipated for a given R
L
.
All actual applications dissipate less power in the output
stage.
Note that it is the power in the output stage and not into the
load that determines internal power dissipation.
As a worst-case example, compute the maximum T
J
using an
OPA847IDBV (SOT23-6 package) in the circuit of Figure 1
operating at the maximum specified ambient temperature of
+85°C and driving a grounded 100
load. Maximum inter-
nal power is:
P
D
= 10V 18.9mA + 5
2
/(4(100
|| 789
)) = 259mW
Maximum T
J
= +85°C + (0.26W 150°C/W) = 124°C
All actual applications will operate at a lower junction tem-
perature than the 124°C computed above. Compute your
actual output stage power to get an accurate estimate of
maximum junction temperature, or use the results shown
here as an absolute maximum.
BOARD LAYOUT
Achieving optimum performance with a high-frequency am-
plifier like the OPA847 requires careful attention to board
layout parasitics and external component types. Recommen-
dations that will optimize performance include:
a) Minimize parasitic capacitance
to any AC ground for all
of the signal I/O pins. Parasitic capacitance on the output and
inverting input pins can cause instability: on the noninverting
input, it can react with the source impedance to cause
unintentional bandlimiting. To reduce unwanted capaci-
tance, create a window around the signal I/O pins in all of the
ground and power planes around these pins. Otherwise,
ground and power planes should be unbroken elsewhere on
the board.
b) Minimize the distance
(< 0.25") from the power-supply
pins to high-frequency 0.1μF decoupling capacitors. At the
device pins, the ground and power plane layout should not
be in close proximity to the signal I/O pins. Avoid narrow
power and ground traces to minimize inductance between
the pins and the decoupling capacitors. The power-supply
connections should always be decoupled with these capaci-
tors. Larger (2.2μF to 6.8μF) decoupling capacitors, effective
at lower frequencies, should also be used on the main supply
pins. These can be placed somewhat further from the device
and can be shared among several devices in the same area
of the PC board.
c) Careful selection and placement of external compo-
nents preserves the high-frequency performance of the
OPA847.
Use resistors that have low reactance at high
frequencies. Surface-mount resistors work best and allow a
tighter overall layout. Metal film and carbon composition
axially leaded resistors can also provide good high-fre-
quency performance. Again, keep their leads and PC board
trace length as short as possible. Never use wirewound type
resistors in a high-frequency application. Since the output pin
and inverting input pin are the most sensitive to parasitic
capacitance, always position the feedback and series output
resistor, if any, as close as possible to the output pin. Other
network components, such as noninverting input termination
resistors, should also be placed close to the package. Where
double-side component mounting is allowed, place the feed-
back resistor directly under the package on the other side of
the board between the output and inverting input pins. Even
with a low parasitic capacitance shunting the external resis-
tors, excessively high resistor values can create significant
time constants that can degrade performance. Good axial
metal film or surface-mount resistors have approximately
0.2pF in shunt with the resistor. For resistor values > 2.0k
,
this parasitic capacitance can add a pole and/or zero below
400MHz that can effect circuit operation. Keep resistor val-
ues as low as possible, consistent with load driving consid-
erations. It has been suggested here that a good starting
point for design would be to set R
G
to 39.2
. Doing this
automatically keeps the resistor noise terms low, and mini-
mizes the effect of their parasitic capacitance. Transimped-
ance applications can use much higher resistor values. The
compensation techniques described in this data sheet allow
excellent frequency response control, even with very high
feedback resistor values.
d) Connections to other wideband devices
on the board
can be made with short, direct traces or through onboard
transmission lines. For short connections, consider the trace
and the input to the next device as a lumped capacitive load.
Relatively wide traces (50mils to 100mils) should be used,
preferably with ground and power planes opened up around
them. Estimate the total capacitive load and set R
S
from the
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| OPA847IDBVR | Wideband, Ultra-Low Noise, Voltage-Feedback |
| OPA847IDBVT | Wideband, Ultra-Low Noise, Voltage-Feedback |
| OPA847IDR | Wideband, Ultra-Low Noise, Voltage-Feedback |
| OPAMP1EVB | Op Amp Evaluation Board Manual SOT23, SC70, and SOIC8 Package |
| OPAMP3EVB | Op Amp Evaluation Board Manual TSSOP−16 Package |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OPA847ID | 功能描述:高速運算放大器 Wdebnd Ult-Lo Noise Voltage Feedback RoHS:否 制造商:Texas Instruments 通道數(shù)量:1 電壓增益 dB:116 dB 輸入補償電壓:0.5 mV 轉(zhuǎn)換速度:55 V/us 工作電源電壓:36 V 電源電流:7.5 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 封裝:Tube |
| OPA847IDBVR | 功能描述:高速運算放大器 Wdebnd Ult-Lo Noise Voltage Feedback RoHS:否 制造商:Texas Instruments 通道數(shù)量:1 電壓增益 dB:116 dB 輸入補償電壓:0.5 mV 轉(zhuǎn)換速度:55 V/us 工作電源電壓:36 V 電源電流:7.5 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 封裝:Tube |
| OPA847IDBVRG4 | 功能描述:高速運算放大器 Wdebnd Ult-Lo Noise Voltage Feedback RoHS:否 制造商:Texas Instruments 通道數(shù)量:1 電壓增益 dB:116 dB 輸入補償電壓:0.5 mV 轉(zhuǎn)換速度:55 V/us 工作電源電壓:36 V 電源電流:7.5 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 封裝:Tube |
| OPA847IDBVT | 功能描述:高速運算放大器 Wdebnd Ult-Lo Noise Voltage Feedback RoHS:否 制造商:Texas Instruments 通道數(shù)量:1 電壓增益 dB:116 dB 輸入補償電壓:0.5 mV 轉(zhuǎn)換速度:55 V/us 工作電源電壓:36 V 電源電流:7.5 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 封裝:Tube |
| OPA847IDBVT | 制造商:Texas Instruments 功能描述:OP AMP WIDEBAND VFB SOT-23-6 847 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。