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SBOS319C SEPTEMBER 2004 REVISED NOVEMBER 2004
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15
dissipation. Superimposing resistor load lines onto the plot
shows that the OPA694 can drive
±
2.5V into 25
or
±
3.5V
into 50
without exceeding the output capabilities or the
1W dissipation limit. A 100
load line (the standard test
circuit load) shows the full
±
3.4V output swing capability,
as shown in the Electrical Charateristics.
The minimum specified output voltage and current
over-temperature are set by worst-case simulations at the
cold temperature extreme. Only at cold startup will the
output current and voltage decrease to the numbers
shown in the Electrical Characteristic tables. As the output
transistors deliver power, the junction temperatures will
increase, decreasing both V
BE
(increasing the available
output voltage swing) and increasing the current gains
(increasing the available output current). In steady-state
operation, the available output voltage and current will
always be greater than that shown in the over-temperature
specifications,
since
the
temperatures will be higher than the minimum specified
operating ambient.
output
stage
junction
DRIVING CAPACITIVE LOADS
One of the most demanding and yet very common load
conditions for an op amp is capacitive loading. Often, the
capacitive load is the input of an ADC—including
additional
external
capacitance
recommended to improve ADC linearity. A high-speed,
high open-loop gain amplifier like the OPA694 can be very
susceptible to decreased stability and closed-loop
response peaking when a capacitive load is placed directly
on the output pin. When the amplifier openloop output
resistance is considered, this capacitive load introduces
an additional pole in the signal path that can decrease the
phase margin. Several external solutions to this problem
have been suggested. When the primary considerations
are frequency response flatness, pulse response fidelity,
and/or distortion, the simplest and most effective solution
is to isolate the capacitive load from the feedback loop by
inserting a series isolation resistor between the amplifier
output and the capacitive load. This does not eliminate the
pole from the loop response, but rather shifts it and adds
a zero at a higher frequency. The additional zero acts to
cancel the phase lag from the capacitive load pole, thus
increasing the phase margin and improving stability.
that
may
be
The Typical Characteristics show the recommended R
S
vs
Capacitive Load and the resulting frequency response at
the load. Parasitic capacitive loads greater than 2pF can
begin to degrade the performance of the OPA694. Long
PC-board traces, unmatched cables, and connections to
multiple devices can easily cause this value to be
exceeded. Always consider this effect carefully, and add
the recommended series resistor as close as possible to
the OPA694 output pin (see the
Board Layout Guidelines
section).
DISTORTION PERFORMANCE
The OPA694 provides good distortion performance into a
100
load on
±
5V supplies. Generally, until the
fundamental signal reaches very high frequency or power
levels, the 2nd-harmonic will dominate the distortion with
a negligible 3rd-harmonic component. Focusing then on
the 2nd-harmonic, increasing the load impedance
improves distortion directly. Remember that the total load
includes the feedback network—in the noninverting
configuration (see Figure 1), this is the sum of R
F
+ R
G
,
while in the inverting configuration it is just R
F
. Also,
providing an additional supply decoupling capacitor
(0.1
μ
F) between the supply pins (for bipolar operation)
improves the 2nd-order distortion slightly (3dB to 6dB).
In most op amps, increasing the output voltage swing
increases harmonic distortion directly. The Typical
Characteristics show the 2nd-harmonic increasing at a
little less than the expected 2x rate, while the 3rd-harmonic
increases at a little less than the expected 3x rate. Where
the test power doubles, the 2nd-harmonic increases by
less than the expected 6dB, while the 3rd-harmonic
increases by less than the expected 12dB. This also
shows up in the 2-tone, 3rd-order intermodulation spurious
(IM3) response curves. The 3rd-order spurious levels are
extremely low at low output power levels. The output stage
continues to hold them low even as the fundamental power
reaches very high levels. As the Typical Characteristics
show, the spurious intermodulation powers do not
increase as predicted by a traditional intercept model. As
the fundamental power level increases, the dynamic range
does not decrease significantly.