
2
OPA688
AC PERFORMANCE (see Figure 1)
Small Signal Bandwidth
V
< 0.2Vp-p
G = +1, R
= 25
G = +2
G = –1
V
< 0.2Vp-p
G = +1, R
F
= 25
, V
O
< 0.2Vp-p
V
< 0.2Vp-p
V
O
= 4Vp-p, V
H
= –V
L
= 2.5V
530
260
230
290
11
50
145
—
150
—
175
—
—
100
—
140
—
170
—
—
95
—
135
—
160
MHz
MHz
MHz
MHz
dB
MHz
MHz
Typ
Min
Typ
Min
Typ
Typ
Min
C
B
C
B
C
C
B
Gain-Bandwidth Product (G
≥
+5)
Gain Peaking
0.1dB Gain Flatness Bandwidth
Large Signal Bandwidth
Step Response:
Slew Rate
Rise/Fall Time
Settling Time: 0.05%
Spurious Free Dynamic Range
Differential Gain
Differential Phase
Input Noise:
Voltage Noise Density
Current Noise Density
—
90
4V Step, V
= –V
L
= 2.5V
0.2V Step
2V Step
f = 5MHz, V
O
= 2Vp-p
NTSC, PAL, R
L
= 500
NTSC, PAL, R
L
= 500
1000
1.2
7
66
0.02
0.01
800
2.6
—
62
—
—
770
2.7
—
58
—
—
650
3
—
53
—
—
V/
μ
s
ns
ns
dB
%
°
Min
Max
Typ
Min
Typ
Typ
B
B
C
B
C
C
f
≥
1MHz
f
≥
1MHz
6.3
2.0
7.2
2.5
7.8
2.9
8
nV/
√
Hz
pA/
√
Hz
Max
Max
B
B
3.6
DC PERFORMANCE (V
= 0)
Open Loop Voltage Gain (A
OL
)
Input Offset Voltage
Average Drift
Input Bias Current
(3)
Average Drift
Input Offset Current
Average Drift
V
O
=
±
0.5V
52
±
2
—
+6
—
±
0.3
—
46
±
6
—
±
12
—
±
2
—
44
±
7
±
14
±
13
–60
±
3
±
10
43
±
9
±
14
±
20
–90
±
4
±
10
dB
mV
μ
V/
°
C
μ
A
nA/
°
C
μ
A
nA/
°
C
Min
Max
Max
Max
Max
Max
Max
A
A
B
A
B
A
B
INPUT
Common-Mode Rejection
Common-Mode Input Range
(4)
Input Impedance
Differential-Mode
Common-Mode
Input Referred, V
CM
=
±
0.5V
57
±
3.3
50
±
3.2
49
±
3.2
47
±
3.1
dB
V
Min
Min
A
A
0.4 || 1
1 || 1
—
—
—
—
—
—
M
|| pF
M
|| pF
Typ
Typ
C
C
OUTPUT
Output Voltage Range
Current Output, Sourcing
V
H
= –V
= 4.3V
R
L
≥
500
V
O
= 0
V
= 0
G = +1, R
F
= 25
, f < 100kHz
±
4.1
105
–85
0.2
±
3.9
90
–70
—
±
3.9
85
–65
—
±
3.8
80
–60
—
V
Min
Min
Min
Typ
A
A
A
C
mA
mA
Sinking
Closed-Loop Output Impedance
POWER SUPPLY
Operating Voltage, Specified
±
5
—
15.8
15.8
—
±
6
17
14
—
±
6
19
12.8
—
±
6
20
11
V
V
Typ
Max
Max
Min
C
A
A
A
Maximum
Quiescent Current, Maximum
mA
mA
Minimum
Power Supply Rejection Ratio
+PSR (Input Referred)
+V
S
= 4.5V to 5.5V
65
58
57
55
dB
Min
A
OUTPUT VOLTAGE LIMITERS
Default Limit Voltage
Minimum Limiter Separation (V
H
– V
L
)
Maximum Limit Voltage
Limiter Input Bias Current Magnitude
(5)
Maximum
Minimum
Average Drift
Limiter Input Impedance
Limiter Feedthrough
(6)
DC Performance in Limit Mode
Limiter Offset
Op Amp Input Bias Current Shift
(3)
AC Performance in Limit Mode
Limiter Small Signal Bandwidth
Limiter Slew Rate
(7)
Limited Step Response
Overshoot
Recovery Time
Linearity Guardband
(8)
Pins 5 and 8
Limiter Pins Open
±
3.3
200
—
±
3.0
200
±
4.3
±
3.0
200
±
4.3
±
2.9
200
±
4.3
V
Min
Min
Max
A
B
B
mV
V
V
O
= 0
54
54
—
65
35
—
—
—
68
34
40
—
—
70
31
45
—
—
μ
A
μ
A
Max
Min
Max
Typ
Typ
A
A
B
C
C
nA/
°
C
M
|| pF
dB
2 || 1
–60
f = 5MHz
V
IN
=
±
2V
(V
O
– V
H
) or (V
O
– V
L
)
±
15
3
±
35
—
±
40
—
±
40
—
mV
μ
A
Max
Typ
A
C
V
IN
=
±
2V, V
O
< 0.02Vp-p
450
100
—
—
—
—
—
—
MHz
V/
μ
s
Typ
Typ
C
C
2x Overdrive
V
IN
= 0 to
±
2V Step
V
IN
=
±
2V to 0V Step
f = 5MHz, V
O
= 2Vp-p
250
2.4
30
—
2.8
—
—
3.0
—
—
3.2
—
mV
ns
mV
Typ
Max
Typ
C
B
C
SPECIFICATIONS—V
S
±
5V
G = +2, R
L
= 500
, R
F
= 402
, V
H
= –V
L
= 2V (Figure 1 for AC performance only), unless otherwise noted.
OPA688U, P
TYP
GUARANTEED
(1)
0
°
C to
+70
°
C
–40
°
C to
+85
°
C
MIN/
MAX
LEVEL
(2)
TEST
PARAMETER
CONDITIONS
+25
°
C
+25
°
C
UNITS