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參數(shù)資料
| 型號(hào)： | OPA682U |
| 英文描述： | Wideband, Fixed Gain BUFFER AMPLIFIER With Disable |
| 中文描述： | 寬帶，固定增益緩沖放大器具有禁用 |
| 文件頁數(shù)： | 18/20頁 |
| 文件大?。?/td> | 213K |
| 代理商： | OPA682U |
18
OPA682
25k
110k
15k
I
Control
–V
S
+V
S
V
DIS
Q1
Dividing this expression by the noise gain (NG = (1+R
F
/R
G
))
will give the equivalent input-referred spot noise voltage at
the non-inverting input as shown in Equation 2.
Evaluating these two equations for the OPA682 circuit and
component values shown in Figure 1 will give a total output
spot noise voltage of 8.4nV/
√
Hz and a total equivalent input
spot noise voltage of 4.2nV/
√
Hz. This total input-referred
spot noise voltage is higher than the 2.2nV/
√
Hz specifica-
tion for the op amp voltage noise alone. This reflects the
noise added to the output by the inverting current noise times
the feedback resistor.
DC ACCURACY
The OPA682 provides exceptional bandwidth in high gains,
giving fast pulse settling but only moderate DC accuracy.
The Typical Specifications show an input offset voltage
comparable to high speed voltage feedback amplifiers. How-
ever, the two input bias currents are somewhat higher and
are unmatched. Bias current cancellation techniques will not
reduce the output DC offset for OPA682. Since the two input
bias currents are unrelated in both magnitude and polarity,
matching the source impedance looking out of each input to
reduce their error contribution to the output is ineffective.
Evaluating the configuration of Figure 1, using worst-case
+25
°
C input offset voltage and the two input bias currents,
gives a worst-case output offset range equal to:
±
(NG V
OS
(max)) + (I
BN
R
S
/2 NG)
±
(I
BI
R
F
)
where NG = non-inverting signal gain
=
±
(2 5.0mV) + (55
μ
A 25
2)
±
(480
40
μ
A)
=
±
10mV + 2.8mV
±
19.2mV
= –26.4mV
→
+32.0mV
Minimizing the resistance seen by the non-inverting input
will give the best DC offset performance.
For significantly improved DC accuracy, consider the preci-
sion buffer circuit shown in Figure 6.
DISABLE OPERATION
The OPA682 provides an optional disable feature that may
be used either to reduce system power or to implement a
simple channel multiplexing operation. If the DIS control
pin is left unconnected, the OPA682 will operate normally.
To disable, the control pin must be asserted low. Figure 8
shows a simplified internal circuit for the disable control
feature.
Eq. 2
E
N
=
E
NI
2
+
I
BN
R
S
(
)
2
+
4kTR
S
+
I
BI
R
F
NG
2
+
4kTR
F
NG
Eq.1
E
O
=
E
NI
2
+
I
BN
R
S
(
)
2
+
4kTR
S
(
)
NG
2
+
I
BI
R
F
(
)
2
+
4kTR
F
NG
FIGURE 8. Simplified Disable Control Circuit.
In normal operation, base current to Q1 is provided through
the 110k
resistor while the emitter current through the
15k
resistor sets up a voltage drop that is inadequate to turn
on the two diodes in Q1’s emitter. As V
DIS
is pulled low,
additional current is pulled through the 15k
resistor even-
tually turning on these two diodes (
≈
100
μ
A). At this point,
any further current pulled out of V
DIS
goes through those
diodes holding the emitter-base voltage of Q1 at approxi-
mately zero volts. This shuts off the collector current out of
Q1, turning the amplifier off. The supply current in the
disable mode is only that required to operate the circuit of
Figure 8. Additional circuitry ensures that turn-on time
occurs faster than turn-off time (make-before-break).
When disabled, the output and input nodes go to a high
impedance state. If the OPA682 is operating in a gain of +1,
this will show a very high impedance (4pF || 1M
) at the
output and exceptional signal isolation. If operating at a gain
of +2, the total feedback network resistance (R
F
+ R
G
) will
appear as the impedance looking back into the output, but
the circuit will still show very high forward and reverse
isolation. If configured at a gain of –1 the input and output
will be connected through the feedback network resistance
(R
F
+ R
G
) giving relatively poor input to output isolation.
One key parameter in disable operation is the output glitch
when switching in and out of the disabled mode. Figure 9
shows these glitches for the circuit of Figure 1 with the input
signal set to zero volts. The glitch waveform at the output pin
is plotted along with the DIS pin voltage.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| OPA682 | Wideband, Fixed Gain BUFFER AMPLIFIER With Disable |
| OPA682N | Wideband, Fixed Gain BUFFER AMPLIFIER With Disable |
| OPA682P | Wideband, Fixed Gain BUFFER AMPLIFIER With Disable |
| OPA686U | Wideband, Low Noise, Voltage Feedback OPERATIONAL AMPLIFIER |
| OPA686N | Wideband, Low Noise, Voltage Feedback OPERATIONAL AMPLIFIER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OPA682U/2K5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog Buffer/Voltage Follower |
| OPA683 | 制造商:BB 制造商全稱:BB 功能描述:Wideband, Low-Power, Current Feedback Operational Amplifier |
| OPA683ID | 功能描述:高速運(yùn)算放大器 Very Lo-Pwr Current Feedback RoHS:否 制造商:Texas Instruments 通道數(shù)量:1 電壓增益 dB:116 dB 輸入補(bǔ)償電壓:0.5 mV 轉(zhuǎn)換速度:55 V/us 工作電源電壓:36 V 電源電流:7.5 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 封裝:Tube |
| OPA683IDBVR | 功能描述:高速運(yùn)算放大器 Very Lo-Pwr Current Feedback RoHS:否 制造商:Texas Instruments 通道數(shù)量:1 電壓增益 dB:116 dB 輸入補(bǔ)償電壓:0.5 mV 轉(zhuǎn)換速度:55 V/us 工作電源電壓:36 V 電源電流:7.5 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 封裝:Tube |
| OPA683IDBVRG4 | 功能描述:高速運(yùn)算放大器 Very Lo-Pwr Current Feedback RoHS:否 制造商:Texas Instruments 通道數(shù)量:1 電壓增益 dB:116 dB 輸入補(bǔ)償電壓:0.5 mV 轉(zhuǎn)換速度:55 V/us 工作電源電壓:36 V 電源電流:7.5 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 封裝:Tube |
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