參數(shù)資料
型號(hào): OPA682
英文描述: Wideband, Fixed Gain BUFFER AMPLIFIER With Disable
中文描述: 寬帶,固定增益緩沖放大器具有禁用
文件頁(yè)數(shù): 17/20頁(yè)
文件大?。?/td> 213K
代理商: OPA682
17
OPA682
4kT
R
G
R
G
R
F
R
S
OPA682
I
BI
E
O
I
BN
4kT = 1.6E –20J
at 290
°
K
E
RS
E
NI
4kTR
S
4kTR
F
leads. This will, under heavy output loads, reduce the avail-
able output voltage swing. A 5
series resistor in each power
supply lead will limit the internal power dissipation to less
than 1W for an output short circuit while decreasing the
available output voltage swing only 0.5V for up to 100mA
desired load currents. Always place the 0.1
μ
F power supply
decoupling capacitors after these supply current limiting
resistors directly on the supply pins.
DRIVING CAPACITIVE LOADS
One of the most demanding and yet very common load
conditions for an op amp is capacitive loading. Often, the
capacitive load is the input of an A/D converter—including
additional external capacitance which may be recommended
to improve A/D linearity. A high-speed amplifier like the
OPA682 can be very susceptible to decreased stability and
frequency response peaking when a capacitive load is placed
directly on the output pin. When the amplifier’s open-loop
output resistance is considered, this capacitive load intro-
duces an additional pole in the signal path that can decrease
the phase margin. Several external solutions to this problem
have been suggested. When the primary considerations are
frequency response flatness, pulse response fidelity and/or
distortion, the simplest and most effective solution is to
isolate the capacitive load from the feedback loop by inserting
a series isolation resistor between the amplifier output and the
capacitive load. This does not eliminate the pole from the loop
response, but rather shifts it and adds a zero at a higher
frequency. The additional zero acts to cancel the phase lag
from the capacitive load pole, thus increasing the phase
margin and improving stability.
The Typical Performance Curves show the recommended R
S
vs Capacitive Load and the resulting frequency response at
the load. Parasitic capacitive loads greater than 2pF can begin
to degrade the performance of the OPA682. Long PC board
traces, unmatched cables, and connections to multiple devices
can easily cause this value to be exceeded. Always consider
this effect carefully, and add the recommended series resistor
as close as possible to the OPA682 output pin (see Board
Layout Guidelines).
DISTORTION PERFORMANCE
The OPA682 provides good distortion performance into a
100
load on
±
5V supplies. Relative to alternative solutions,
it provides exceptional performance into lighter loads and/or
operating on a single +5V supply. Generally, until the funda-
mental signal reaches very high frequency or power levels, the
2nd harmonic will dominate the distortion with a negligible
3rd harmonic component. Focusing then on the 2nd harmonic,
increasing the load impedance improves distortion directly.
Remember that the total load includes the feedback network-
in the non-inverting configuration (Figure 1) this is the sum of
R
F
+ R
G
, while in the inverting configuration it is just R
F
. Also,
providing an additional supply decoupling capacitor (0.1
μ
F)
between the supply pins (for bipolar operation) improves the
2nd-order distortion slightly (3dB to 6dB).
In most op amps, increasing the output voltage swing in-
creases harmonic distortion directly. The Typical Performance
Curves show the 2nd harmonic increasing at a little less than
the expected 2X rate while the 3rd harmonic increases at a
little less than the expected 3X rate. Where the test power
doubles, the difference between it and the 2nd harmonic
decreases less than the expected 6dB while the difference
between it and the 3rd decreases by less than the expected
12dB. This also shows up in the 2-tone, 3rd-order
intermodulation spurious (IM3) response curves. The 3rd-
order spurious levels are extremely low at low output power
levels. The output stage continues to hold them low even as
the fundamental power reaches very high levels. As the
Typical Performance Curves show, the spurious
intermodulation powers do not increase as predicted by a
traditional intercept model. As the fundamental power level
increases, the dynamic range does not decrease significantly.
For two tones centered at 20MHz, with 10dBm/tone into a
matched 50
load (i.e., 2Vp-p for each tone at the load, which
requires 8Vp-p for the overall 2-tone envelope at the output
pin), the Typical Performance Curves show 62dBc difference
between the test-tone power and the 3rd-order intermodulation
spurious levels. This exceptional performance improves fur-
ther when operating at lower frequencies.
NOISE PERFORMANCE
The OPA682 offers an excellent balance between voltage and
current noise terms to achieve low output noise. The inverting
current noise (15pA/
Hz) is significantly lower than earlier
solutions while the input voltage noise (2.2nV
Hz) is lower
than most unity gain stable, wideband, voltage feedback op
amps. This low input voltage noise was achieved at the price
of higher non-inverting input current noise (12pA/
Hz). As
long as the AC source impedance looking out of the non-
inverting node is less than 100
, this current noise will not
contribute significantly to the total output noise. The op amp
input voltage noise and the two input current noise terms
combine to give low output noise for the gain settings,
available using the OPA682. Figure 7 shows the op amp noise
analysis model with all the noise terms included. In this
model, all noise terms are taken to be noise voltage or current
density terms in either nV/
Hz or pA/
Hz.
The total output spot noise voltage can be computed as the
square root of the sum of all squared output noise voltage
contributors. Equation 1 shows the general form for the output
noise voltage using the terms shown in Figure 7.
FIGURE 7. Noise Model.
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