- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄363780 > OPA642U Wideband, Low Distortion, Low Gain OPERATIONAL AMPLIFIER PDF資料下載
參數(shù)資料
| 型號： | OPA642U |
| 元件分類： | 運(yùn)算放大器 |
| 英文描述： | Wideband, Low Distortion, Low Gain OPERATIONAL AMPLIFIER |
| 中文描述： | 寬帶，低失真，低增益運(yùn)算放大器 |
| 文件頁數(shù)： | 13/15頁 |
| 文件大?。?/td> | 243K |
| 代理商： | OPA642U |
OPA642
13
FIGURE 8. DC Coupled, Inverting Gain of –2, with Output
Offset Adjustment.
closest integer for minimum noise figure. This optimum
turns ratio is calculated by
This optimum will depend strongly on the amplifier and
configuration selected.
the offset control is best applied as an inverting summing
signal. If the signal path is intended to be inverting, applying
the offset control to the non-inverting input can be consid-
ered. For a DC coupled signal, the DC offset signal can, in
some configurations, set up a DC current back into the
source that must be considered. An adjustment placed on the
inverting op amp input can also change the noise gain and
frequency response flatness. Figure 8 shows one example of
an offset adjustment for a DC coupled signal path that will
have minimum impact on the signal frequency response. In
this case, the input is brought in to an inverting gain resistor
with the DC adjustment an additional current summed into
the inverting node. The resistor network setting this current
is much larger than the signal path resistors. This will insure
that this adjustment has minimal impact on the loop gain and
hence the frequency response.
FIGURE 7. Reduced Noise Figure Circuit.
DC OFFSET CONTROL
The OPA642 can provide excellent DC signal accuracy due
to its high open-loop gain, high common-mode rejection,
high power supply rejection, and low input offset voltage
and bias current offset errors. The high grade (B) version of
any package type provides less than 1mV input offset
voltage. To take full advantage of this low input offset
voltage, a careful attention to input bias current cancellation
is also required. The high speed input stage for the OPA642
has a relatively high input bias current (25
μ
A typ into the
pins) but with a very close match between the two input
currents—typically 100nA input offset current. The total
output offset voltage may be considerably reduced by match-
ing the source impedances looking out of the two inputs. For
example, one way to add bias current cancellation to the
circuit of Figure 1 would be to insert a 175
series resistor
into the non-inverting input from the 50
terminating resis-
tor. When the 50
source resistor is DC coupled, this will
increase the source impedance for the non-inverting input
bias current to 200
. Since this is now equal to the imped-
ance looking out of the inverting input (R
F
|| R
G
), the circuit
will cancel the gains for the bias currents to the output
leaving only the offset current times the feedback resistor as
a residual DC error term at the output. Using a 402
feedback resistor, this output error will now be less than 3
μ
A
402
= 1.2mV.
A fine scale output offset null, or DC operating point
adjustment, is sometimes required. Numerous techniques
are available for introducing a DC offset control into an op
amp circuit. Most of these techniques eventually reduce to
setting up a DC current through the feedback resistor. One
key consideration to selecting a technique is to insure that it
has a minimal impact on the desired signal path frequency
response. If the signal path is intended to be non-inverting,
R
F
1k
±200mV Output Adjustment
= – R
G
Supply Decoupling
Not Shown
5k
5k
328
0.1μF
R
G
500
V
I
20k
10k
0.1μF
–5V
+5V
OPA642
+5V
–5V
V
O
V
O
V
I
R
F
THERMAL ANALYSIS
The OPA642 will not require heatsinking under most oper-
ating conditions. Maximum desired junction temperature
will set a maximum allowed internal power dissipation as
described below. In no case should the maximum junction
temperature be allowed to exceed 175
°
C.
Operating junction temperature (T
J
) is given by
T
A
+ P
D
θ
JA
. The total internal power dissipation (P
D
) is the
sum of quiescent power (P
DQ
) and additional power dissi-
pated in the output stage (P
DL
) to deliver load power.
Quiescent power is simply the specified no-load supply
current times the total supply voltage across the part. P
DL
will depend on the required output signal and load but
would, for a grounded resistive load, be at a maximum when
the output is fixed at a voltage equal to 1/2 either supply
voltage (for equal bipolar supplies). Under this condition
P
DL
= V
S2
/(4 R
L
) where R
L
includes feedback network
loading.
Eq. 4
N
OPT
=
Nearest Integer
E
N
/ I
BN
R
S
/ 2
(
(
)
)
402
50
A
V
= 7V/V [16.9dB]
Supply Decoupling
Not Shown
6.3dB
Noise Figure
R
S
= 50
1:7
OPA642
402
2.4k
50
Load
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| OPA642NB | Wideband, Low Distortion, Low Gain OPERATIONAL AMPLIFIER |
| OPA642UB | Wideband, Low Distortion, Low Gain OPERATIONAL AMPLIFIER |
| OPA643 | Wideband Low Distortion, High Gain OPERATIONAL AMPLIFIER |
| OPA643N | Wideband Low Distortion, High Gain OPERATIONAL AMPLIFIER |
| OPA643P | Wideband Low Distortion, High Gain OPERATIONAL AMPLIFIER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OPA642UB | 制造商:Texas Instruments 功能描述:Operational Amplifier, Single AMP, Bipolar, 8 Pin, Plastic, SOP |
| OPA643 | 制造商:BB 制造商全稱:BB 功能描述:Wideband Low Distortion, High Gain OPERATIONAL AMPLIFIER |
| OPA643N | 制造商:BB 制造商全稱:BB 功能描述:Wideband Low Distortion, High Gain OPERATIONAL AMPLIFIER |
| OPA643N/250 | 功能描述:IC OPAMP VFB 800MHZ SGL SOT23-5 RoHS:否 類別:集成電路 (IC) >> Linear - Amplifiers - Instrumentation 系列:- 產(chǎn)品變化通告:Discontinuation 18/May/2012 標(biāo)準(zhǔn)包裝:2,000 系列:- 放大器類型:通用 電路數(shù):4 輸出類型:滿擺幅 轉(zhuǎn)換速率:0.42 V/µs 增益帶寬積:1.5MHz -3db帶寬:- 電流 - 輸入偏壓:15nA 電壓 - 輸入偏移:1000µV 電流 - 電源:116µA 電流 - 輸出 / 通道:100mA 電壓 - 電源，單路/雙路(±):1.8 V ~ 5 V，±0.9 V ~ 2.5 V 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:14-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:14-TSSOP 包裝:帶卷 (TR) 產(chǎn)品目錄頁面:851 (CN2011-ZH PDF) 其它名稱:296-20930-2 |
| OPA643N/3K | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。