參數(shù)資料
型號(hào): OPA632N
英文描述: Low Power, Single-Supply OPERATIONAL AMPLIFIERS TM
中文描述: 低功耗,單電源運(yùn)算放大器商標(biāo)
文件頁數(shù): 11/17頁
文件大?。?/td> 176K
代理商: OPA632N
11
OPA631, OPA632
APPLICATIONS INFORMATION
WIDEBAND VOLTAGE-FEEDBACK OPERATION
The OPA631 and OPA632 are unity-gain stable, very high-
speed, voltage-feedback op amps designed for single-supply
operation (+3V to +5V). The input stage supports input
voltages below ground, and within 1.0V of the positive
supply. The complementary common-emitter output stage
provides an output swing to within 30mV of ground and
130mV of the positive supply. They are compensated to
provide stable operation with a wide range of resistive loads.
The OPA632’s internal disable circuitry is intended to mini-
mize system power when disabled.
Figure 1 shows the AC-coupled, gain of +2 configuration
used for the +5V Specifications and Typical Performance
Curves. For test purposes, the input impedance is set to 50
with a resistor to ground. Voltage swings reported in the
Specifications are taken directly at the input and output pins.
For the circuit of Figure 1, the total effective load on the
output at high frequencies is 150
|| 1500
. The disable pin
(OPA635 only) needs to be driven by a low impedance
source, such as a CMOS inverter. The 1.50k
resistors at
the non-inverting input provide the common-mode bias
voltage. Their parallel combination equals the DC resistance
at the inverting input, minimizing the output DC offset.
SINGLE-SUPPLY ADC CONVERTER INTERFACE
The front page shows a DC-coupled, single-supply ADC
driver circuit. Many systems are now requiring +3V supply
capability of both the ADC and its driver. The OPA632
provides excellent performance in this demanding applica-
tion. Its large input and output voltage ranges, and low
distortion, support converters such as the ADS901 shown in
this figure. The input level-shifting circuitry was designed
so that V
IN
can be between 0V and 0.5V, while delivering an
output voltage of 1V to 2V for the ADS901. Both the
OPA632 and ADS901 have power reduction pins with the
same polarity for those systems that need to conserve power.
DC LEVEL SHIFTING
Figure 3 shows a DC-coupled non-inverting amplifier that
level-shifts the input up to accommodate the desired output
voltage range. Given the desired signal gain (G), and the
amount V
OUT
needs to be shifted up (
V
OUT
) when V
IN
is at
the center of its range, the following equations give the
resistor values that produce the best DC offset.
NG = G +
V
OUT
/V
S
R
1
= R
4
/G
R
2
= R
4
/(NG – G)
R
3
= R
4
/(NG –1)
where:
NG = 1 + R
4
/R
3
(Noise Gain)
V
OUT
= (G)V
IN
+ (NG – G)V
S
Make sure that V
IN
and V
OUT
stay within the specified input
and output voltage ranges.
Figure 2 shows the DC-coupled, gain of +2 configuration
used for the +3V Specifications and Typical Performance
Curves. For test purposes, the input impedance is set to 50
with a resistor to ground. Though not strictly a “rail-to-rail”
design, these parts come very close, while maintaining
excellent performance. They will deliver
2.9Vp-p on a
single +3V supply with 61MHz bandwidth. The 374
and
2.26k
resistors at the input level-shift V
IN
so that V
OUT
is
within the allowed output voltage range when V
IN
= 0. See
the Typical Performance Curves for information on driving
capacitive loads.
FIGURE 1. AC-Coupled Signal—Resistive Load to Supply
Midpoint.
FIGURE 2. DC-Coupled Signal—Resistive Load to Supply
Midpoint.
OPA63x
+V
S
= 5V
DIS (OPA632 only)
V
OUT
53.6
V
IN
750
1.50k
1.50k
R
L
150
+V
S
2
750
6.8
μ
F
+
0.1
μ
F
0.1
μ
F
0.1
μ
F
+
OPA63x
+V
S
= 3V
DIS (OPA632 only)
V
OUT
57.6
V
IN
562
374
2.26k
R
L
150
+V
S
2
750
6.8
μ
F
+
0.1
μ
F
+
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