
"#$
SBOS319C SEPTEMBER 2004 REVISED NOVEMBER 2004
www.ti.com
17
OPA694
180
2.86k
20
DIS
+5V
5V
V
O
Powersupply
decoupling not shown.
OPA237
5V
+5V
V
I
18k
2k
1.8k
Figure 11. Wideband, DC-Connected Composite
Circuit
This DC-coupled circuit provides very high signal
bandwidth using the OPA694. At lower frequencies, the
output voltage is attenuated by the signal gain and
compared to the original input voltage at the inputs of the
OPA237 (this is a low-cost, precision voltage-feedback op
amp with 1.5MHz gain bandwidth product). If these two do
not agree (due to DC offsets introduced by the OPA694),
the OPA237 sums in a correction current through the
2.86k
inverting summing path. Several design
considerations will allow this circuit to be optimized. First,
the feedback to the OPA237 noninverting input must be
precisely matched to the high-speed signal gain. Making
the 2k
resistor to ground an adjustable resistor would
allow the low- and high-frequency gains to be precisely
matched. Second, the crossover frequency region where
the OPA237 passes control to the OPA694 must occur with
exceptional phase linearity. These two issues reduce to
designing for pole/zero cancellation in the overall transfer
function. Using the 2.86k
resistor will nominally satisfy
this requirement for the circuit in Figure 11. Perfect
cancellation over process and temperature is not possible.
However, this initial resistor setting and precise gain
matching will minimize long-term pulse settling tails.
THERMAL ANALYSIS
Due to the high output power capability of the OPA694,
heatsinking or forced airflow may be required under
extreme operating conditions. Maximum desired junction
temperature will set the maximum allowed internal power
dissipation, as described below. In no case should the
maximum junction temperature be allowed to exceed
150
°
C.
Operating junction temperature (T
J
) is given by T
A
+ P
D
×
θ
JA
.
The total internal power dissipation (P
D
) is the sum of
quiescent power (P
DQ
) and additional power dissipated in
the output stage (P
DL
) to deliver load power. Quiescent
power is simply the specified no-load supply current times
the total supply voltage across the part. P
DL
will depend on
the required output signal and load but would, for a grounded
resistive load, be at a maximum when the output is fixed at
a voltage equal to 1/2 either supply voltage (for equal bipolar
supplies). Under this condition P
DL
= V
S2
/(4
×
R
L
) where R
L
includes feedback network loading.
Note that it is the power in the output stage and not in the
load that determines internal power dissipation.
As a worst-case example, compute the maximum T
J
using
an OPA694IDBV (SOT23-5 package) in the circuit of
Figure 1 operating at the maximum specified ambient
temperature of +85
°
C and driving a grounded 20
load to
+2.5V DC:
P
D
= 10V
×
6.0mA + 5
2
/(4
×
(20
|| 804
)) = 380m
Maximum T
J
= +85
°
C + (0.38W
×
(150
°
C/W) = 142
°
C
Although this is still below the specified maximum junction
temperature, system reliability considerations may require
lower junction temperatures. Remember, this is a
worst-case internal power dissipation—use your actual
signal and load to compute P
DL
. The highest possible
internal dissipation will occur if the load requires current to
be forced into the output for positive output voltages or
sourced from the output for negative output voltages. This
puts a high current through a large internal voltage drop in
the output transistors. The
Output Voltage and Current
Limitations
plot shown in the Typical Characteristics
includes a boundary for 1W maximum internal power
dissipation under these conditions.