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參數(shù)資料
| 型號(hào)： | OPA2734AIDGSTG4 |
| 元件分類： | 音頻放大器 |
| 英文描述： | Single Audio Amplifier |
| 中文描述： | 單音頻放大器 |
| 文件頁數(shù)： | 8/23頁 |
| 文件大?。?/td> | 615K |
| 代理商： | OPA2734AIDGSTG4 |
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SBOS282B DECEMBER 2003 REVISED FEBRUARY 2005
APPLICATIONS INFORMATION
www.ti.com
8
The OPA734 and OPA735 series of op amps are
unity-gain stable and free from unexpected output phase
reversal. They use auto-zeroing techniques to provide low
offset voltage and demonstrate very low drift over time and
temperature.
Good layout practice mandates the use of a 0.1
μ
F
capacitor placed closely across the supply pins.
For lowest offset voltage and precision performance,
circuit layout and mechanical conditions should be
optimized. Avoid temperature gradients that create
thermoelectric (Seebeck) effects in thermocouple
junctions formed from connecting dissimilar conductors.
These thermally-generated potentials can be made to
cancel by assuring that they are equal on both input
terminals:
1.
Use low thermoelectric-coefficient connections
(avoid dissimilar metals).
2.
Thermally isolate components from power supplies
or other heat sources.
3.
Shield op amp and input circuitry from air currents
such as cooling fans.
Following these guidelines will reduce the likelihood of
junctions being at different temperatures, which can cause
thermoelectric voltages of 0.1
μ
V/
°
C or higher, depending
on the materials used.
OPERATING VOLTAGE
The OPA734 and OPA735 op amp family operates with a
power-supply range of +2.7V to +12V (
±
1.35V to
±
6V).
Supply voltages higher than +13.2V (absolute maximum)
can permanently damage the amplifier. Parameters that
vary over supply voltage or temperature are shown in the
Typical Characteristics section of this data sheet.
OPA734 ENABLE FUNCTION
The enable/shutdown digital input is referenced to the V
supply voltage of the op amp. A logic HIGH enables the op
amp. A valid logic HIGH is defined as > (V) + 2V. The valid
logic HIGH signal can be up to the positive supply,
independent of the negative power supply voltage. A valid
logic LOW is defined as < 0.8V above the V supply pin.
If dual or split power supplies are used, be sure that logic
input signals are properly referred to the negative supply
voltage. The Enable pin is connected to internal pull-up
circuitry and will enable the device if this pin is left open
circuit.
The logic input is a CMOS input. Separate logic inputs are
provided for each op amp on the dual version. For
battery-operated applications, this feature can be used to
greatly reduce the average current and extend battery life.
The enable time is 150
μ
s, which includes one full
auto-zero cycle required by the amplifier to return to V
OS
accuracy. Prior to returning to full accuracy, the amplifier
may function properly, but with unspecified offset voltage.
Disable time is 1.5
μ
s. When disabled, the output assumes
a high-impedance state. The disable state allows the
OPA734 to be operated as a gated amplifier, or to have the
output multiplexed onto a common analog output bus.
INPUT VOLTAGE
The input common-mode range extends from (V) 0.1V
to (V+) 1.5V. For normal operation, the inputs must be
limited to this range. The common-mode rejection ratio is
only valid within the specified input common-mode range.
A lower supply voltage results in lower input common-
mode range; therefore, attention to these values must be
given when selecting the input bias voltage. For example,
when operating on a single 3V power supply, common-
mode range is from 0.1V below ground to half the
power-supply voltage.
Normally, input bias current is approximately 100pA;
however, input voltages exceeding the power supplies can
cause excessive current to flow in or out of the input pins.
Momentary voltages greater than the power supply can be
tolerated if the input current is limited to 10mA. This is
easily accomplished with an input resistor, as shown in
Figure 1.
50
OPA735
+5V
V
IN
V
OUT
10mA max
I
OVERLOAD
Currentlimited resistor required
if input voltage exceeds supply
rails by
≥
0.5V.
Figure 1. Input Current Protection
INTERNAL OFFSET CORRECTION
The OPA734 and OPA735 series of op amps use an
auto-zero topology with a time-continuous 1.6MHz op amp
in the signal path. This amplifier is zero-corrected every
100
μ
s using a proprietary technique. Upon power-up, the
amplifier requires one full auto-zero cycle of approximately
100
μ
s in addition to the start-up time for the bias circuitry
to achieve specified V
OS
accuracy. Prior to this time, the
amplifier may function properly but with unspecified offset
voltage.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OPA2735AID | 功能描述:運(yùn)算放大器 - 運(yùn)放 0.05uV/degC single- supply CMOS RoHS:否 制造商:STMicroelectronics 通道數(shù)量:4 共模抑制比（最小值）:63 dB 輸入補(bǔ)償電壓:1 mV 輸入偏流（最大值）:10 pA 工作電源電壓:2.7 V to 5.5 V 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-16 轉(zhuǎn)換速度:0.89 V/us 關(guān)閉:No 輸出電流:55 mA 最大工作溫度:+ 125 C 封裝:Reel |
| OPA2735AIDG4 | 功能描述:運(yùn)算放大器 - 運(yùn)放 0.05uV/degC single- supply CMOS RoHS:否 制造商:STMicroelectronics 通道數(shù)量:4 共模抑制比（最小值）:63 dB 輸入補(bǔ)償電壓:1 mV 輸入偏流（最大值）:10 pA 工作電源電壓:2.7 V to 5.5 V 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-16 轉(zhuǎn)換速度:0.89 V/us 關(guān)閉:No 輸出電流:55 mA 最大工作溫度:+ 125 C 封裝:Reel |
| OPA2735AIDGKR | 功能描述:運(yùn)算放大器 - 運(yùn)放 0.05uV/degC single- supply CMOS RoHS:否 制造商:STMicroelectronics 通道數(shù)量:4 共模抑制比（最小值）:63 dB 輸入補(bǔ)償電壓:1 mV 輸入偏流（最大值）:10 pA 工作電源電壓:2.7 V to 5.5 V 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-16 轉(zhuǎn)換速度:0.89 V/us 關(guān)閉:No 輸出電流:55 mA 最大工作溫度:+ 125 C 封裝:Reel |
| OPA2735AIDGKRG4 | 功能描述:運(yùn)算放大器 - 運(yùn)放 0.05uV/degC single- supply CMOS RoHS:否 制造商:STMicroelectronics 通道數(shù)量:4 共模抑制比（最小值）:63 dB 輸入補(bǔ)償電壓:1 mV 輸入偏流（最大值）:10 pA 工作電源電壓:2.7 V to 5.5 V 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-16 轉(zhuǎn)換速度:0.89 V/us 關(guān)閉:No 輸出電流:55 mA 最大工作溫度:+ 125 C 封裝:Reel |
| OPA2735AIDGKT | 功能描述:運(yùn)算放大器 - 運(yùn)放 0.05uV/degC single- supply CMOS RoHS:否 制造商:STMicroelectronics 通道數(shù)量:4 共模抑制比（最小值）:63 dB 輸入補(bǔ)償電壓:1 mV 輸入偏流（最大值）:10 pA 工作電源電壓:2.7 V to 5.5 V 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-16 轉(zhuǎn)換速度:0.89 V/us 關(guān)閉:No 輸出電流:55 mA 最大工作溫度:+ 125 C 封裝:Reel |
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