參數(shù)資料
型號: OM6211
廠商: NXP Semiconductors N.V.
英文描述: 48 X 84 dot matrix LCD driver
中文描述: 48 × 84點陣LCD驅(qū)動器
文件頁數(shù): 24/48頁
文件大?。?/td> 243K
代理商: OM6211
2002 Jan 17
24
Philips Semiconductors
Product specification
48
×
84 dot matrix LCD driver
OM6211
Notes
1.
V
DD2
is always equal V
DD3
.
Conditions are: V
DD2
= 2.5 V, voltage multiplier = 3V
DD2
, bias system
1
6
, V
LCD
output is loaded by 10
μ
A,
T
amb
= 25
°
C.
Valid for values of temperature, V
PR
and TC used at the calibration.
Conditionsare: V
DD1
= 1.8 V,V
DD2
= 2.78 V, V
LCD
= 6.8 V,voltage multiplier = 3V
DD2
,bias system
1
6
, inputs atV
DD1
or V
SS
, serial interface inactive, internal V
LCD
generation, V
LCD
output is loaded by 10
μ
A; T
amb
= 25
°
C.
Conditionsare: V
DD1
= 1.8 V,V
DD2
= 2.78 V, V
LCD
= 8.3 V,voltage multiplier = 4V
DD2
,bias system
1
7
, inputs atV
DD1
or V
SS
, serial interface inactive, internal V
LCD
generation, V
LCD
output is loaded by 10
μ
A; T
amb
= 25
°
C.
Load current 10
μ
A, outputs tested one at a time.
2.
3.
4.
5.
6.
Logic
V
IL
V
IH
I
OL
I
OH
I
L
Column and row outputs
LOW-level input voltage
HIGH-level input voltage
LOW-level output current (SDOUT)
HIGH-level output current (SDOUT)
leakage current
V
SS
0.7V
DD1
0.5
1
0.3V
DD1
V
V
DD1
0.5
+1
V
mA
mA
μ
A
V
OL
= 0.4 V; V
DD1
= 1.8 V
V
OH
= 1.4 V; V
DD1
= 1.8 V
V
I
= V
DD1
or V
SS
R
o(col)
column output resistance (COL 0 to
COL 83)
row output resistance (ROW 0 to
ROW 47)
bias tolerance (COL 0 to COL 83)
bias tolerance (ROW 0 to ROW 47)
note 6
4
20
k
R
o(row)
note 6
4
20
k
V
bias(col)
V
bias(row)
Calibration inputs
100
100
0
0
+100
+100
mV
mV
R
on(Vos)
external resistance between a V
OS
pin
and the V
SS1
pin for logic 0
external resistance between a V
OS
pin
and the V
SS1
pin for logic 1
10
k
R
off(Vos)
5
M
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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