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參數(shù)資料
| 型號(hào)： | OM4085 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Universal LCD driver for low multiplex rates |
| 中文描述： | 通用LCD驅(qū)動(dòng)器的低復(fù)用率 |
| 文件頁(yè)數(shù)： | 25/36頁(yè) |
| 文件大?。?/td> | 225K |
| 代理商： | OM4085 |
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1997 Feb 25
25
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
OM4085
DC CHARACTERISTICS
V
SS
= 0 V; V
DD
= 2.0 to 6 V; V
LCD
= V
DD
2.0 to V
DD
6 V; T
amb
=
40 to +85
°
C; unless otherwise specified.
Notes
1.
2.
3.
4.
Outputs open; inputs at V
SS
or V
DD
; external clock with 50% duty factor; I
2
C-bus inactive.
Resets all logic when V
DD
< V
ref
.
Periodically sampled, not 100% tested.
Outputs measured one at a time.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
V
DD
V
LCD
I
DD
operating supply voltage
LCD supply voltage
operating supply current
(normal mode)
power saving mode supply current
2.0
V
DD
6
30
6
V
DD
2.0 V
90
V
f
CLK
= 200 kHz; note 1
μ
A
I
LP
V
DD
= 3.5 V; V
LCD
= 0 V;
f
CLK
= 35 kHz; A0,
A1 and A2 tied to V
SS
;
note 1
15
40
μ
A
Logic
V
IL
V
IH
V
OL
V
OH
I
OL1
LOW level input voltage
HIGH level input voltage
LOW level output voltage
HIGH level output voltage
LOW level output current
(CLK and SYNC)
HIGH level output current (CLK)
LOW level output current
(SDA and SCL)
leakage current
(SA0, CLK, OSC, A0, A1, A2, SCL
and SDA)
pull-down current
(A0, A1, A2 and OSC)
pull-up resistor (SYNC)
power-on reset level
tolerable spike width on bus
input capacitance
V
SS
0.7V
DD
V
DD
0.05
1
0.3V
DD
V
DD
0.05
V
V
V
V
mA
I
O
= 0 mA
I
O
= 0 mA
V
OL
= 1 V; V
DD
= 5 V
I
OH
I
OL2
V
OH
= 4 V; V
DD
= 5 V
V
OL
= 0.4 V; V
DD
= 5 V
3
1
mA
mA
I
LI
V
I
= V
SS
or V
DD
±
1
μ
A
I
pd
V
I
= 1 V; V
DD
= 5 V
15
50
150
μ
A
R
puSYNC
V
ref
t
sw
C
i
15
25
1.3
60
2
100
7
k
V
ns
pF
note 2
note 3
LCD outputs
V
BP
DC voltage component
(BP0 to BP3)
DC voltage component (S0 to S23)
output impedance (BP0 to BP3)
output impedance (S0 to S23)
C
BP
= 35 nF
±
20
mV
V
S
Z
BP
Z
S
C
S
= 5 nF
V
LCD
= V
DD
5 V; note 4
V
LCD
= V
DD
5 V; note 4
±
20
1
3
5
7
mV
k
k
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