參數(shù)資料
型號(hào)： OM4068U
廠商： NXP SEMICONDUCTORS
元件分類： 顯示驅(qū)動(dòng)器
英文描述： LCD driver for low multiplex rates
中文描述： LIQUID CRYSTAL DISPLAY DRIVER, UUC
封裝： DIE
文件頁(yè)數(shù)： 13/28頁(yè)
文件大小： 156K
代理商： OM4068U
1998 Jun 18
13
Philips Semiconductors
Product specification
LCD driver for low multiplex rates
OM4068
Oscillator
The internal logic and the multi-level LCD drive signals of
the OM4068 are generated by the built-in RC oscillator.
No external components are required.
In order to minimize radio frequency interference, the
oscillator operates with symmetrical and slew-rate limited
capacitor charge/discharge.
The oscillator runs continuously once the power down
state after power-on has been left.
Interface to microprocessor unit: serial interface
A three-line bus structure enables serial unidirectional
data transfer with microprocessors/microcontrollers.
The three lines are a serial data input line (SDIN), a serial
clock line (SCLK) and a data line enable (SCE). All inputs
are CMOS compatible. These lines must always be in a
defined state V
SS
or V
DD
.Floating inputs could damage the
chip.
On the bus, one data bit is transferred during each clock
pulse. The data on the SDIN line remains stable during the
whole clock period. Data changes arrive with the falling
edge of the serial clock SCLK (see Fig.8).
Fig.8 Bit transfer on bus.
handbook, full pagewidth
MBK822
data line
stable;
data valid
change
of data
allowed
SDIN
SDOUT
SCLK
Shift register
Data present on the SDIN pin is shifted into a shift register
with the rising edge of the serial clock SCLK in a
synchronous manner. The shift register serves to transfer
display information from the serial bus to the (display) latch
while previous data is displayed.
The shift register is organized as three 32-bit shift
registers. Depending on the display driving mode selected
(see Table 3), one, two or three registers are used and
cascaded resulting in a shift register length of 32, 64 or
96 bits. Figure 9 shows the shift register organization with
the display data bits after a shift operation is completed.
The shift sequence begins with data bit D32 and finishes
with data bit D1. The correspondence between the data bit
numbers and the LCD display segments is shown in
Table 4.
Data from the last stage of the register is supplied to the
SDOUT pin to allow serial cascading of the OM4068 with
other peripheral devices. Depending on the display driving
mode selected, SDOUT corresponds to bit 32, 64 or 96 of
the register (see Fig.10). Data on the SDOUT pin is shifted
out with the falling edge of the SCLK clock. SDOUT is
therefore delayed by
1
2
SCLK cycle before it is applied to
the SDIN pin of the next IC in the serial chain (see Fig.8).
The clock enable SCE signal must be HIGH in order to
enable the shift operation. SDOUT output is latched with
the last data after SCE returned to HIGH (shift operation
terminated).
SDOUT is in 3-state mode when SCE is LOW.
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