參數(shù)資料
型號: NTE6821
廠商: NTE Electronics, Inc.
英文描述: Integrated Circuit Peripheral Interface Adapter (PIA), NMOS, 1MHz
中文描述: 集成電路外設(shè)接口適配器(PIA)的,NMOS管,1MHz的
文件頁數(shù): 3/5頁
文件大?。?/td> 45K
代理商: NTE6821
Bus Timing Characteristics (Cont’d):
(V
CC
= 5V
±
5%, V
SS
= 0, T
A
= 0
°
to +70
°
C unless otherwise
specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Setup Time, Address and R/W Valid to
Enable Positive Transition
Address Hold Time
t
AS
160
ns
t
AH
t
DDR
t
DHR
t
DSW
t
DHW
10
ns
Data Delay Time, Read
320
ns
Data Hold Time, Read
10
ns
Data Setup Time, Write
195
ns
data Hold Time, Write
10
ns
Peripheral Timing Characteristics:
(V
CC
= 5V
±
5%, V
SS
= 0, T
A
= 0
°
to +70
°
C unless otherwise
specified)
Parameter
Symbol
Min
Max
Unit
Peripheral Data Setup Time
t
PDSU
t
PDH
t
CA2
t
RS1
t
r
, t
f
t
RS2
t
PDW
t
CMOS
t
CB2
t
DC
t
RS1
PW
CT
t
r
, t
f
t
RS2
t
IR
t
RS3
PW
I
t
RL
200
ns
Peripheral Data Hold Time
0
ns
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
ns
μ
s
ns
μ
s
μ
s
μ
s
μ
s
ns
μ
s
Delay Time, Enable negative transition to CA2 negative transition
1.0
Delay Time, Enable negative transition to CA2 positive transition
1.0
Rise and fall Times for CA1 and CA2 input signals
1.0
Delay Time from CA1 active transition to CA2 positive transition
2.0
Delay Time, Enable negative transition to Peripheral Data Valid
1.0
Delay Time, Enable negative transition to Peripheral CMOS Data Valid PA0
PA7, CA2
2.0
Delay Time, Enable positive transition to CB2 negative transition
1.0
Delay Time, Peripheral Data Valid to CB2 negative transition
20
Delay Time, Enable positive transition to CB2 postivie transition
1.0
Peripheral Control Output Pulse Width, CA2/CB2
550
Rise and Fall Time for CB1 and CB2 input signals
1.0
Delay Time, CB1 active transition to CB2 positive transition
2.0
Interrupt Release Time, IRQA and IRQB
2.0
Interrupt Response Time
1.0
Interrupt Input Pulse Width
500
Reset Low Time (Note 2)
1.0
Note 2. The Reset line must be high a minimum of 1.0
μ
s before addressing the PIA.
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