<big id="rnmoo"><sup id="rnmoo"><ins id="rnmoo"></ins></sup></big>
  • <thead id="rnmoo"></thead>
    <dl id="rnmoo"><span id="rnmoo"><pre id="rnmoo"></pre></span></dl>
    <ins id="rnmoo"></ins>
    參數(shù)資料
    型號: NTD25P03LG
    廠商: ON SEMICONDUCTOR
    元件分類: JFETs
    英文描述: Power MOSFET
    中文描述: 25 A, 30 V, 0.08 ohm, P-CHANNEL, Si, POWER, MOSFET
    封裝: LEAD FREE, CASE 369C-01, DPAK-3
    文件頁數(shù): 4/10頁
    文件大?。?/td> 74K
    代理商: NTD25P03LG
    NTD25P03L
    http://onsemi.com
    4
    POWER MOSFET SWITCHING
    Switching behavior is most easily modeled and predicted
    by recognizing that the power MOSFET is charge
    controlled. The lengths of various switching intervals ( t)
    are determined by how fast the FET input capacitance can
    be charged by current from the generator.
    The published capacitance data is difficult to use for
    calculating rise and fall because draingate capacitance
    varies greatly with applied voltage. Accordingly, gate
    charge data is used. In most cases, a satisfactory estimate of
    average input current (I
    G(AV)
    ) can be made from a
    rudimentary analysis of the drive circuit so that
    t = Q/I
    G(AV)
    During the rise and fall time interval when switching a
    resistive load, V
    GS
    remains virtually constant at a level
    known as the plateau voltage, V
    SGP
    . Therefore, rise and fall
    times may be approximated by the following:
    t
    r
    = Q
    2
    x R
    G
    /(V
    GG
    V
    GSP
    )
    t
    f
    = Q
    2
    x R
    G
    /V
    GSP
    where
    V
    GG
    = the gate drive voltage, which varies from zero to V
    GG
    R
    G
    = the gate drive resistance
    and Q
    2
    and V
    GSP
    are read from the gate charge curve.
    During the turnon and turnoff delay times, gate current is
    not constant. The simplest calculation uses appropriate
    values from the capacitance curves in a standard equation for
    voltage change in an RC network. The equations are:
    t
    d(on)
    = R
    G
    C
    iss
    In [V
    GG
    /(V
    GG
    V
    GSP
    )]
    t
    d(off)
    = R
    G
    C
    iss
    In (V
    GG
    /V
    GSP
    )
    The capacitance (C
    iss
    ) is read from the capacitance curve at
    a voltage corresponding to the offstate condition when
    calculating t
    d(on)
    and is read at a voltage corresponding to the
    onstate when calculating t
    d(off)
    .
    At high switching speeds, parasitic circuit elements
    complicate the analysis. The inductance of the MOSFET
    source lead, inside the package and in the circuit wiring
    which is common to both the drain and gate current paths,
    produces a voltage at the source which reduces the gate drive
    current. The voltage is determined by Ldi/dt, but since di/dt
    is a function of drain current, the mathematical solution is
    complex. The MOSFET output capacitance also
    complicates the mathematics. And finally, MOSFETs have
    finite internal gate resistance which effectively adds to the
    resistance of the driving source, but the internal resistance
    is difficult to measure and, consequently, is not specified.
    The resistive switching time variation versus gate
    resistance (Figure 9) shows how typical switching
    performance is affected by the parasitic circuit elements. If
    the parasitics were not present, the slope of the curves would
    maintain a value of unity regardless of the switching speed.
    The circuit used to obtain the data is constructed to minimize
    common inductance in the drain and gate circuit loops and
    is believed readily achievable with board mounted
    components. Most power electronic loads are inductive; the
    data in the figure is taken with a resistive load, which
    approximates an optimally snubbed inductive load. Power
    MOSFETs may be safely operated into an inductive load;
    however, snubbing reduces switching losses.
    Figure 7. Capacitance Variation
    10
    15
    20
    10
    5
    5
    0
    25
    1200
    1000
    800
    600
    400
    200
    0
    GATETOSOURCE OR DRAINTOSOURCE
    VOLTAGE (VOLTS)
    C
    C
    rss
    C
    iss
    C
    oss
    C
    rss
    T
    J
    = 25
    °
    C
    V
    DS
    = 0 V
    V
    GS
    V
    DS
    1400
    2200
    2000
    V
    GS
    = 0 V
    C
    iss
    1600
    1800
    相關(guān)PDF資料
    PDF描述
    NTD25P03LT4 Power MOSFET
    NTD3055-150 Power MOSFET 9.0Amps, 60Volts N-Channel DPAK(9.0A, 60V,N通道,DPAK封裝的功率MOSFET)
    NTD3055L104 Power MOSFET
    NTD3055L104G Power MOSFET
    NTD3055L104T4 Power MOSFET
    相關(guān)代理商/技術(shù)參數(shù)
    參數(shù)描述
    NTD25P03LG 制造商:ON Semiconductor 功能描述:P CHANNEL MOSFET -30V -25A D-PAK 制造商:ON Semiconductor 功能描述:P CHANNEL MOSFET, -30V, -25A, D-PAK
    NTD25P03LRL 功能描述:MOSFET -30V -25A P-Channel RoHS:否 制造商:STMicroelectronics 晶體管極性:N-Channel 汲極/源極擊穿電壓:650 V 閘/源擊穿電壓:25 V 漏極連續(xù)電流:130 A 電阻汲極/源極 RDS(導(dǎo)通):0.014 Ohms 配置:Single 最大工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:Max247 封裝:Tube
    NTD25P03LRLG 功能描述:MOSFET PFET 30V 25A LL TR RoHS:否 制造商:STMicroelectronics 晶體管極性:N-Channel 汲極/源極擊穿電壓:650 V 閘/源擊穿電壓:25 V 漏極連續(xù)電流:130 A 電阻汲極/源極 RDS(導(dǎo)通):0.014 Ohms 配置:Single 最大工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:Max247 封裝:Tube
    NTD25P03LT4 功能描述:MOSFET -30V -25A P-Channel RoHS:否 制造商:STMicroelectronics 晶體管極性:N-Channel 汲極/源極擊穿電壓:650 V 閘/源擊穿電壓:25 V 漏極連續(xù)電流:130 A 電阻汲極/源極 RDS(導(dǎo)通):0.014 Ohms 配置:Single 最大工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:Max247 封裝:Tube
    NTD25P03LT4G 功能描述:MOSFET -30V -25A P-Channel RoHS:否 制造商:STMicroelectronics 晶體管極性:N-Channel 汲極/源極擊穿電壓:650 V 閘/源擊穿電壓:25 V 漏極連續(xù)電流:130 A 電阻汲極/源極 RDS(導(dǎo)通):0.014 Ohms 配置:Single 最大工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:Max247 封裝:Tube