
NT7502
Reset Circuit
When the RES input falls to “L”, these LSI reenter their default state. The default settings are shown below:
1. Display OFF
2. Normal display
3. ADC select: Normal display (ADC command D0 = “L”)
4. Power control register (D2, D1, D0) = (0, 0, 0,)
5. Register data clear in serial interface
6. LCD power supply bias ratio 1/9 (1/65 duty), 1/8 (1/55, 1/49 duty), 1/6 (1/33 duty)
7. Read modify write OFF
8. Static indicator: OFF
Static indicator register: (D1, D2) = (0, 0)
9. Display start line register set at first line
10. Column address counter set at address0
11. Page address register set at page 0
12. Common output status normal
13. V0 voltage regulator internal power supply ratio set mode clear:
V0 voltage regulator internal resistor ratio register: (D2, D1, D0) = (1, 0, 0)
14. Electronic volume register set mode clear
Electronic volume register: (D5, D4, D3, D2, D1, D0) = (1, 0, 0, 0, 0, 0,)
15. Test mode clear
16. All-indicator-lamps-on OFF (All-indicator-lamps ON/OFF command D0 = “L”)
17. Output condition of COM, SEG
COM:
V1
SEG:
V2
On the other hand, when the reset command is used, only default settings 7 to 15 above are put into effect.
The MPU interface (Reference Example)”, the RES terminal is connected to the MPU reset terminal, making the chip
reinitialize simultaneously with the MPU. At the time of power up, it is necessary to reinitialize using the RES terminal.
Moreover, when the control signal from the MPU is in a high impedance state, there may be an overcurrent condition; therefore,
take measures to prevent the input terminal from entering a high impedance state.
In the NT7502, if the internal liquid crystal power supply circuit is not used, then it is necessary to apply a “L” signal to the RES
terminal when the external liquid crystal power supply is applied.
Even though the oscillator circuit operates while the RES terminal is “L,” the display timing generator circuit is stopped, and the
FR, FRS, and DOF terminals are fixed to “H,” and the CL pin is fixed to “H” only when the intermal oscillator circuit is used.
There is no influence on the D0 to D7 terminals.
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