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參數(shù)資料
| 型號(hào)： | NT7181 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | LVDS Transmitter 24 Bit Color Host-LCD Display Panel Interface |
| 中文描述： | LVDS發(fā)送主機(jī)24位彩色液晶顯示面板接口 |
| 文件頁(yè)數(shù)： | 7/15頁(yè) |
| 文件大?。?/td> | 360K |
| 代理商： | NT7181 |
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6 Swing Characteristics Over Recommended Operating Conditions
Symbol
t
d0
t
d1
Parameter
Min.
-0.4
1.8
Typ.*
Max.
0.3
2.5
Unit
ns
ns
ns
ns
ns
ns
ns
Conditions
Delay Time, TCLK
↓
to Serial Bit Position 0
Delay Time, TCLK
↓
to Serial Bit Position 1
t
d2
Delay Time, TCLK
↓
to Serial Bit Position 2
4.0
4.7
t
d3
Delay Time, TCLK
↓
to Serial Bit Position 3
6.2
6.9
t
d4
Delay Time, TCLK
↓
to Serial Bit Position 4
8.4
9.1
t
d5
Delay Time, TCLK
↓
to Serial Bit Position 5
10.6
11.3
t
d6
Delay Time, TCLK
↓
to Serial Bit Position 6
12.8
13.5
t
c
= 15.38 ns (
±
0.2%),
|
Input Clock Jitter
|
< 50
ps**
See Figure 5
t
c
= 15.38 ns (
±
0.2%),
|
Input Clock Jitter
|
< 50
ps **
See Figure 5
t
d7
Delay Time, CLKIN
↑
or CLKIN
↓
to TCLK
↑
3.0
4.2
5.5
ns
t
w
Pulse Duration, High-Level Output Clock
0.35t
c
7
4
t
c
0.65t
c
ns
t
t
Transition Time, Differential Output Voltage
(t
r
or t
f
)
260
700
1500
ps
See Figure 2
t
en
Enable Time,
PWDN
↑
to Phase Lock
(TCLK Valid)
10
ms
See Figure 6
t
dis
Disable Time,
PWDN
↓
to Off State (TCLK
Low)
100
ns
See Figure 7
* All typical values are at VCC = 3.3V, T
A
= 25
°
C
**
|
Input Clock Jitter
|
is the magnitude of the change in the input clock period.
7
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