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參數(shù)資料
| 型號： | NT68P62 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 8-Bit Microcontroller for Monitor (32K OTP ROM Type) |
| 中文描述： | 8位微控制器的監(jiān)視器（32K的檢察官辦公室光盤形式） |
| 文件頁數(shù)： | 40/56頁 |
| 文件大小： | 528K |
| 代理商： | NT68P62 |
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NT68P62-01
40
15.3. DDC2B Slave Mode Bus Interface
Enable I
2
C and INTS: After user clears the
NT68P62 will enter into DDC1 mode, and it will switch to
DDC2B SLAVE mode while a low pulse is detected on SCL
line. The DDC2B bus consists of two wires, SCL and SDA;
SCL is the data transmission clock and SDA is the data
line. NT68P62 will remind user that the mode has changed
by generating a INTS interrupt. When users set MD1/
'1' at this time, the NT68P62 will return back to DDC1
mode. (For DDC2B please refer to Figure 15.2.) The figure
exhibits what are important in I
2
C: START signal, slave
ADDRESS, transferred data (proceed byte by byte) and a
STOP signal.
to ‘0’,
to
Start condition: When SCL & SDA lines are at HIGH state,
an external device (master) may initiate communication by
sending a START signal (defined as SDA from high to low
transition while SCL is at high state). When there is a
START condition, NT68P62 will set the 'START' bit to '1'
and user can poll this status bit to control DDC2B
transmission at any time. This bit will keep '1' until user
clears it. After sending a START signal for DDC2B
communication, an external device can repeatedly send
start condition without sending a STOP signal to terminate
this communication. This is used by external device to
communicate with another slave or with the same slave in
different mode (Read or Write mode) without releasing the
bus.
Address matched and INTA0: After the START condition, a
slave address is sent by an external device. When I
2
C bus
interface changes to DDC2B mode, NT68P62 will act as a
receiver first to receive this one byte data. This address
data is 7 bits long followed by the eighth bit (R/W) that
indicates data transfer direction. When the NT68P62
system receives an address data from an external device, it
will store it in the CH0RXDAT register. The system
supports 'A0' default address and another one set of
addresses which can be accessed by writting the
CH0ADDR register. Upon receiving the calling address
from an external device, the system will compare this
received data with the default 'A0' address and data in the
CH0ADDR register. Either of these address matched, the
system will set the INTA0 bit in the IRQ0 register. If the
user sets INTA0 bit to '1' (in IEIRQ0 register) in advanced
and addresses match, the NT68P62 will generate a INTA0
interrupt. Under the address matching condition, the
NT68P62 will send an acknowledge bit to an external
device. If address does not match, the NT68P62 will not
generate INTA0 interrupt and neglect the data change on
SDA line in the future.
Data transmission direction: In INTA0 interrupt servicing
routine, user must check the LSB of address data in
CH0RXDAT register. According to I
2
C bus protocol, this bit
indicates the DDC2B data transfer direction in later
transmission; '1' indicates a request for 'READ MODE'
action (external master device read data from system), '0'
indicates a 'WRITE MODE' action (external master device
write data to system). The timing about READ mode and
WRITE mode please refer to Figure 15.3 and Figure 15.4.
The data transfer can proceeded byte by byte in a direction
specified by the R/
bit after a successful slave address
is received.
The system will switch to either 'READ' mode or 'WRITE'
mode automatically
which is determined by this direction
bit.
Figure 15.5. DDC Structure Block
TXDAT
TXACK
9 bits Shift Register
Compare Logic
ADDR
RXDAT
INTA
ENDDC
in
out
clk
INTTX
INTRX
INTNAK
DDC2BR [2..0]
Clock Generator
SDA
VSYNC
SCL
INTS
MODE
MD1/2
R/W
STOP Detector
INTSTOP
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