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參數(shù)資料
| 型號： | NT68F62U |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 8-Bit Microcontroller for Monitor (32K Flash MTP Type) |
| 中文描述： | 8位微控制器的監(jiān)視器（32K閃存中期型） |
| 文件頁數(shù)： | 36/57頁 |
| 文件大?。?/td> | 521K |
| 代理商： | NT68F62U |
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NT68F62
36
1
2
3
4
9
1
2
3
4
5
6
7
INTV
8
9
1
2
Vsync Pulse
ENDDC
(in CH0CON register)
INTTX
8
7
6
8
7
6
5
4
3
2
1
Shift
register
SDA
1
8
7
Null
Bit
5
4
3
1
8
6
2
Null
Bit
●
●
●
5
7
MSB
LSB
Second Byte Data
First Byte Data
Invalid data
User can load next byte data
to CH0TXDAT register
Load data in the CH0TXDAT
register to shift register
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
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Figure 15.1. DDC1 Mode Timing Diagram
15.2. DDC2B + Slave & Master Mode Bus Interface
The built-in DDC2B+ IIC bus Interface features are as follows:
SLAVE mode (NT68F62 is addressed by a master that
drives SCL signal)
-
MASTER mode (NT68F62 addresses external
devices and sends out the SCL clock)
-
Compatible with IIC bus standard
-
One default $A0 slave address ( can be disabled ) and
one user programmable address
-
Automatic wait state insertion
-
Interrupt generation for status control
-
Detection of START and STOP signals
The DDC2B+ will be activated as SLAVE mode initially.
Users can switch to MASTER mode by clearing the
MODE
bit under either of these conditions listed as follows:
1. After entering into DDC1 function and clearing this bit,
the system will be changed from DDC1 to DDC2B+
MASTER mode operation.
2. After entering into DDC2B+ slave mode function and
clearing this bit, the system will be changed from slave
mode into master mode operation.
During clearing of the
MODE
bit, the system will send out a
'START' condition and wait for the user to put the calling
address into the CH0/1TXDAT control register. Notice: the
user must predetermine the direction of the master mode
transmission before putting the calling address.
Below is the DDC2B+ function with channel 0, and the
manipulation of channel 1 is the same as channel 0.
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