參數(shù)資料
型號(hào): NT6868AH
廠商: Electronic Theatre Controls, Inc.
英文描述: Keyboard Controller
中文描述: 鍵盤控制器
文件頁(yè)數(shù): 5/14頁(yè)
文件大?。?/td> 205K
代理商: NT6868AH
NT6868A
5
Timing Generation
This block generates the system timing and control
signal supplied to CPU and on-chip peripherals. There
are two types of system clock sources: built-in RC
oscillator or external ceramic resonator. Both of them are
mask optional and generate a 4MHz system clock. They
also generates 2MHz for CPU, and 1MHz for base timer.
The following shows the relationship of code type
number and oscillation type.
Oscillator Type
Code Number
RC OSC
1
Ceramic Resonator
3
The following table provides the relationship between
external resistor and RC OSC frequency. (for reference
only)
External Resistor
(K
W
)
RC OSC Frequency (MHz)
39
4.7
43
4.44
47
4
56
3.68
Base Timer
The base timer is an 8-bit counter with a 1MHz clock source. The base timer can be enabled/disabled by CPU. After reset,
the base timer is disabled and cleared. The base timer can be preset by writing BT7 - BT0 to the BT register at any time.
When enabled, the base timer starts counting from the preset value. When the value reaches FFH, it generates a timer
interrupt if the timer interrupt is enabled. When it reaches the maximum value of FFH, the base timer will wrap around and
begin counting at 00H. The timer interval can be programmed from 1 - 256
μ
sec. The base timer can be enabled by writing
a '0' to '
ENBT
' in the TCON (Timer Control) register. The
ENBT
is a level trigger.
Base timer structure:
8-Bit timer
BT7
BT6
BT5
BT4
BT2
BT2
BT1
BT0
BT pre-load data:
Addr.
$00C0
Bit
BT
7
6
5
4
3
2
1
0
BT7
BT6
BT5
BT4
BT3
BT2
BT1
BT0
(W)
Timer Control Regisrer:
$00C1
TCON
-
-
-
-
-
-
-
ENBT
(W)
INT. Controller
When BASE TIMER overflow occurs, it will set the IRQTMR flag. The IRQTMR flag cannot be directly accessed by
software. Once set by an interrupt source, it remains High unless cleared by writing '1' to the corresponding bit in
CLRIRQX ($00C2H). This register is cleared to '0' on initialization by system reset.
When an interrupt occurs, CPU jumps to $FFFEH & $FFFFH to execute the interrupt service routine. When BASE TIMER
interrupt occurs and enters the interrupt service routine, the IRQTMR flag must be cleared by software.
Interrupt Control Register:
Addr.
$00C2
Bit
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
CLRIRQX
CLRIRQTMR
(W)
1
μ
s
TMRINT
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