參數(shù)資料
型號: NT5SV8M8DT
廠商: Electronic Theatre Controls, Inc.
英文描述: 64Mb Synchronous DRAM
中文描述: 64Mb的同步DRAM
文件頁數(shù): 18/21頁
文件大?。?/td> 203K
代理商: NT5SV8M8DT
NT5SV16M4DT
NT5SV8M8DT
NT5SV4M16DT
64Mb Synchronous DRAM
REV 1.1
10/01
18
NANYA TECHNOLOGY CORP
. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Read Cycle
Symbol
Parameter
-6K
-7K
-7
Units
Notes
Min.
Max.
Min.
Max.
Min.
Max.
t
OH
Data Out Hold Time
ns
1
3
3
3
ns
2, 4
t
LZ
Data Out to Low Impedance Time
0
0
ns
t
HZ3
Data Out to High Impedance Time
2.7
5.4
2.7
5.4
2.7
5.4
ns
3
t
HZ2
Data Out to High Impedance Time
2.7
5.4
2.7
5.4
3
6
ns
3
t
DQZ
DQM Data Out Disable Latency
2
2
2
CK
1. AC Output Load Circuit A.
2. AC Output Load Circuit B.
3. Referenced to the time at which the output achieves the open circuit condition, not to output voltage levels.
4. Data Out Hold Time with no load must meet 1.8ns (-5K, -7K, -75B).
Refresh Cycle
Symbol
Parameter
-6K
-7K
-7
Units
Notes
Min.
Max.
Min.
Max.
Min.
Max.
t
REF
Refresh Period
64
64
64
ms
1
t
SREX
Self Refresh Exit Time
10
10
10
ns
1. 4096 auto refresh cycles.
Write Cycle
Symbol
Parameter
-6K
-7K
-7
Units
Min.
Max.
Min.
Max.
Min.
Max.
t
DS
Data In Set-up Time
1.5
1.5
1.5
ns
t
DH
Data In Hold Time
0.8
0.8
0.8
ns
t
DPL
Data input to Precharge
12
14
14
ns
t
WR
Write Recovery Time
12
14
14
ns
t
DAL3
Data In to Active Delay
CAS Latency = 3
5
5
5
CK
t
DAL2
Data In to Active Delay
CAS Latency = 2
4
4
4
CK
t
DQW
DQM Write Mask Latency
0
0
CK
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