參數(shù)資料
型號(hào)： NT5SV8M8DT-7K
廠商： Electronic Theatre Controls, Inc.
英文描述： 64Mb Synchronous DRAM
中文描述： 64Mb的同步DRAM
文件頁(yè)數(shù)： 15/21頁(yè)
文件大?。?/td> 203K
代理商： NT5SV8M8DT-7K
NT5SV16M4DT
NT5SV8M8DT
NT5SV4M16DT
64Mb Synchronous DRAM
REV 1.1
10/01
15
NANYA TECHNOLOGY CORP
. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Operating, Standby, and Refresh Currents
(T
A
= 0 to +70
°
C, V
DD
= 3.3V
±
0.3V)
Parameter
Symbol
Test Condition
-6K
-7K
-7
Units
Notes
(6ns)
(7ns)
(7ns)
Operating Current
I
CC1
1 bank operation
t
= t
(min), t
= min
Active-Precharge command cycling
without burst operation
60
55
mA
1, 2, 3
Precharge Standby Current
in Power Down Mode
I
CC2P
CKE
≤
V
IL
(max), t
CK
= min,
CS = V
IH
(min)
CKE
≤
V
IL
(max), t
CK
= Infinity,
CS = V
IH
(min)
CKE
≥
V
IH
(min), t
CK
= min,
CS = V
IH
(min)
CKE
≥
V
IH
(min), t
CK
= Infinity,
CKE
≥
V
IH
(min), t
CK
= min,
CS = V
IH
(min)
CKE
≤
V
IL
(max), t
CK
= min,
1
mA
1
I
CC2PS
1
mA
1
Precharge Standby Current
in Non-Power Down Mode
I
CC2N
10
mA
1, 5
I
CC2NS
5
mA
1, 7
No Operating Current
(Active state: 4 bank)
I
CC3N
30
mA
1, 5
I
CC3P
9
mA
1, 6
Operating Current (Burst
Mode)
I
CC4
t
CK
= min,
Read/ Write command cycling,
Multiple banks active, gapless data,
BL = 4
75
70
mA
1, 3, 4
Auto (CBR) Refresh Current
I
CC5
t
= min, t
= t
(min)
CBR command cycling
120
110
mA
1
Self Refresh Current
I
CC6
CKE
≤
0.2V
1
mA
1
1. Currents given are valid for a single device. The total current for a stacked device depends on the operation being performed
on the other deck.
2. These parameters depend on the cycle rate and are measured with the cycle determined by the minimum value of t
CK
and t
RC
.
Input signals are changed up to three times during t
RC
(min).
3. The specified values are obtained with the output open.
4. Input signals are changed once during t
CK
(min).
5. Input signals are changed once during three clock cycles.
6. Active Standby Current will be higher if Clock Suspend is entered during a burst read cycle (add 1mA per DQ).
7. Input signals are stable.
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