- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄363669 > NT5SV32M8AT (Electronic Theatre Controls, Inc.) 256Mb Synchronous DRAM PDF資料下載
參數(shù)資料
| 型號： | NT5SV32M8AT |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 256Mb Synchronous DRAM |
| 中文描述： | 256Mb的同步DRAM |
| 文件頁數(shù)： | 21/65頁 |
| 文件大?。?/td> | 814K |
| 代理商： | NT5SV32M8AT |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁當前第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁
NT5SV64M4AT(L)
NT5SV32M8AT(L)
NT5SV16M16AT(L)
256Mb Synchronous DRAM
REV 1.0
May, 2001
21
NANYA TECHNOLOGY CORP
. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Precharge Command
The Precharge Command is used to precharge or close a bank that has been activated. The Precharge Command is triggered
when CS, RAS, and WE are low and CAS is high at the rising edge of the clock. The Precharge Command can be used to pre-
charge each bank separately or all banks simultaneously. Three address bits, A10, BA0, and BA1, are used to define which
bank(s) is to be precharged when the command is issued.
For read cycles, the Precharge Command may be applied (CAS latency - 1) prior to the last data output. For write cycles, a
delay must be satisfied from the start of the last burst write cycle until the Precharge Command can be issued. This delay is
known as t
DPL
, Data-in to Precharge delay.
After the Precharge Command is issued, the precharged bank must be reactivated before a new read or write access can be
executed. The delay between the Precharge Command and the Activate Command must be greater than or equal to the Pre-
charge time (t
RP
).
Burst Write with Auto-Precharge Interrupted by Read
Bank Selection for Precharge by Address Bits
A10
Bank Select
Precharged Bank(s)
LOW
BA0, BA1
Single bank defined by BA0, BA1
HIGH
DON’ T CARE
All Banks
DIN A
0
COMMAND
NOP
NOP
NOP
Auto-Precharge
DIN A
1
CK
T0
T2
T1
T3
T4
T5
T6
T7
T8
NOP
NOP
*
NOP
t
CK3
,
DQs
CAS latency = 3
Bank A can be reactivated at completion of t
DAL
.
t
DAL
is a function of clock cycle time and speed sort.
*
READ B
DIN A
2
NOP
DOUT B
0
DOUT B
1
DOUT B
2
t
DAL
(Burst Length = 4, CAS Latency = 3)
See the Clock Frequency and Latency table.
相關PDF資料 |
PDF描述 |
|---|---|
| NT5SV32M8AT-75B | 256Mb Synchronous DRAM |
| NT5SV32M8AT-7K | 256Mb Synchronous DRAM |
| NT5SV32M8AT-8B | 256Mb Synchronous DRAM |
| NT5SV64M4AT | 256Mb Synchronous DRAM |
| NT5SV64M4AT-7K | 256Mb Synchronous DRAM |
相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NT5SV32M8AT-75B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:256Mb Synchronous DRAM |
| NT5SV32M8AT-7K | 制造商:Nanya Technology Corporation 功能描述:32M X 8 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| NT5SV32M8AT-8B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:256Mb Synchronous DRAM |
| NT5SV4M16DT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64Mb Synchronous DRAM |
| NT5SV4M16DT-6K | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64Mb Synchronous DRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復。