參數(shù)資料
型號(hào): NT5DS64M4AW-8B
廠商: Electronic Theatre Controls, Inc.
英文描述: 256Mb Double Data Rate SDRAM
中文描述: 256MB雙數(shù)據(jù)速率SDRAM
文件頁數(shù): 39/78頁
文件大小: 1534K
代理商: NT5DS64M4AW-8B
NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb Double Data Rate SDRAM
REV 1.1
12/2001
39
NANYA TECHNOLOGY CORP
. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Write to Read: Nominal DQSS, Interrupting (CAS Latency = 2; Burst Length = 8)
T1
T2
T3
T4
T5
T6
t
DQSS
(nom)
NOP
NOP
NOP
Read
Write
NOP
DI a-b = data in for bank a, column b.
An interrupted burst is shown, 4 data elements are written.
3 subsequent elements of data in are applied in the programmed order following DI a-b.
t
WTR
is referenced from the first positive CK edge after the last desired data in pair.
The Read command masks the last 2 data elements in the burst.
A10 is Low with the Write command (Auto Precharge is disabled).
The Read and Write commands are not necessarily to the same bank.
1 = These bits are incorrectly written into the memory array if DM is low.
DI a-b
CK
CK
Command
Address
DQS
DQ
DM
Don’t Care
BAa, COL b
BAa, COL n
t
WTR
CL = 2
1
1
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