
NT3883
4
Absolute Maximum Ratings*
Power Supply Voltage (V
DD
-GND) . . . . . . -0.3V to 7.0V
Power Supply Voltage (V
DD
-V
EE
) . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . .V
DD
- 13.5V to V
DD
+ 0.3V
Input Voltage . . . . . . . . . . . . . . -0.3V to V
DD
+ 0.3V
Operating Temperature . . . . . . . . . . -20
q
C to + 75
q
C
Storage Temperature . . . . . . . . . . . . . -55
q
C to + 125
q
C
*Comments
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of
this device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied and exposure to the absolute maximum
rating conditions for extended periods may affect device
reliability.
DC Electrical Characteristics
(V
DD
= 5.0V, GND = 0V, V
EE
= 0V, T
A
= 25
q
C)
Parameter
Symbol
Terminal
Min.
Typ.
Max.
Unit
Conditions
Input Voltage
V
IH
0.7 V
DD
-
V
DD
V
V
IL
CL1, CL2,
DL1, DL2
*1
0
-
0.3 V
DD
V
Output Voltage
V
OH
DR1, DR2
*1
V
DD
- 0.4
-
-
V
I
OH
= -0.4mA
V
OL
-
-
0.4
V
I
OL
= +0.4mA
Vi - Sj Voltage
V
D1
-
-
1.1
V
I
ON
= 0.1mA for one of Sj
Descending
V
D2
*2
-
-
1.5
V
I
ON
= 0.05mA for each of Sj
Input Leakage
Current
I
IL
CL1, CL2
DL1,
DL2*1
-5
-
5
P
A
V
IN
= 0 or V
DD
Vi Leakage
Current
I
VL
V
2
, V
3
, V
EE
-10
-
10
P
A
S1 to S80 open
Power Supply
Current
I
DD
*3
-
-
500
P
A
f
CL1
= 1KHz
f
CL2
= 1MHz
Note *1: SL1 and SL2 determine The Input or Output of DL1, DL2, DR1 and DR2 and the configuration is as follows.
Terminal
DL1
DR1
DL2
DR2
SL1 = High
Output
Input
-
-
SL1 = Low
Input
Output
-
-
SL2 = High
-
-
Output
Input
SL2 = Low
-
-
Input
Output
*2: V
i
– S
j
(V
i
= V
DD
, V
2
, V
3
, V
EE
; j = 1 to 80) equivalent circuit (for reference)
*3: Input/output current is excluded. When the input is at the intermediate level with CMOS, some excessive
V
i
1Kmax.
10Kmax.
Power
Switch
Data
Swtich
S
j
Current will flow through the input circuit to power supply. To avoid this, the input level must be fixed at high or
low state.