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參數(shù)資料
| 型號(hào)： | NT256D64S8HA0G-7K |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 184pin Two Bank Unbuffered DDR SDRAM MODULE |
| 中文描述： | 184pin兩個(gè)銀行無緩沖DDR SDRAM內(nèi)存模塊 |
| 文件頁數(shù)： | 3/13頁 |
| 文件大小： | 203K |
| 代理商： | NT256D64S8HA0G-7K |
NT256D64S8HA0G
256MB : 32M x 64
PC2100 / PC1600 Unbuffered DIMM
Input/Output Functional Description
Symbol
Type
Preliminary
3
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Polarity
Function
CK0 , CK1, CK2
(SSTL)
Positive
Edge
The positive line of the differential pair of system clock inputs which drives the input to the
on-DIMM PLL. All the DDR SDRAM address and control inputs are sampled on the rising
edge of their associated clocks.
The negative line of the differential pair of system clock inputs which drives the input to the
on-DIMM PLL.
Activates the SDRAM CK signal when high and deactivates the CK signal when low. By
deactivating the clocks, CKE low initiates the Power Down mode, or the Self Refresh
mode.
Enables the associated SDRAM command decoder when low and disables the command
decoder when high. When the command decoder is disabled, new commands are ignored
but previous operations continue.
When sampled at the positive rising edge of the clock,
RAS
,
CAS
,
WE
define the
operation to be executed by the SDRAM.
Reference voltage for SSTL-2 inputs
Isolated power supply for the DDR SDRAM output buffers to provide improved noise
immunity
Selects which SDRAM bank is to be active.
During a Bank Activate command cycle, A0-A11 defines the row address (RA0-RA11)
when sampled at the rising clock edge.
During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9)
when sampled at the rising clock edge. In addition to the column address, AP is used to
invoke Autoprecharge operation at the end of the Burst Read or Write cycle. If AP is high,
autoprecharge is selected and BA0/BA1 define the bank to be precharged. If AP is low,
autoprecharge is disabled.
During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control
which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the
state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to pre-charge.
Data and Check Bit input/output pins operate in the same manner as on conventional
DRAMs.
Data strobes: Output with read data, input with write data. Edge aligned with read data,
centered on write data. Used to capture write data.
Power and ground for the DDR SDRAM input buffers and core logic
Address inputs. Connected to either VDD or VSS on the system board to configure the
Serial Presence Detect EEPROM address.
This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor
must be connected from the SDA bus line to V
DD
to act as a pullup.
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be
connected from the SCL bus time to V
DD
to act as a pullup.
Serial EEPROM positive power supply.
CK0
,
CK1
,
CK2
(SSTL)
Negative
Edge
CKE0, CKE1
(SSTL)
Active
High
S0
,
S1
(SSTL)
Active
Low
RAS
,
CAS
,
WE
(SSTL)
Active
Low
V
REF
Supply
V
DDQ
Supply
BA0, BA1
(SSTL)
-
A0 - A9
A10/AP
A11
(SSTL)
-
DQ0 - DQ63,
(SSTL)
-
DQS0 - DQS7
DQS9 - DQS16
(SSTL)
Active
High
V
DD
, V
SS
Supply
SA0 – SA2
-
SDA
-
SCL
-
V
DDSPD
Supply
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| NT256D64S8HA0G-8B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:184pin Two Bank Unbuffered DDR SDRAM MODULE |
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| NT256D64SH8B0GM-75B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:200pin Unbuffered DDR SO-DIMM |
| NT256D72S890G-5T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:184 pin Unbuffered DDR DIMM |
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