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參數(shù)資料
| 型號(hào)： | NT256D64S88A0G |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 184pin One Bank Unbuffered DDR SDRAM MODULE |
| 中文描述： | 一位銀行無緩沖184pin DDR SDRAM內(nèi)存模塊 |
| 文件頁數(shù)： | 11/14頁 |
| 文件大?。?/td> | 211K |
| 代理商： | NT256D64S88A0G |
NT256D64S88A0G
256MB : 32M x 64
PC2100 / PC1600 Unbuffered DIMM
AC Timing Specifications for DDR SDRAM Devices Used on Module
( T
A
= 0 °C ~ 70 °C ; V
DDQ
= 2.5V ± 0.2V; V
DD
= 2.5V ± 0.2V, See AC Characteristics)
(Part 1 of 2)
Preliminary
08 / 2001
11
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
-7K
-75B
-8B
Symbol
Parameter
Min.
-0.75
-0.75
0.45
0.45
7
7.5
Max.
+0.75
+0.75
0.55
0.55
12
12
Min.
-0.75
-0.75
0.45
0.45
7.5
10
Max.
+0.75
+0.75
0.55
0.55
12
12
Min.
-0.8
-0.8
0.45
0.45
8
10
Max.
+0.8
+0.8
0.55
0.55
12
12
Unit
Notes
t
AC
DQ output access time from CK/
CK
DQS output access time from CK/
CK
CK high-level width
CK low-level width
ns
ns
t
CK
t
CK
ns
ns
1,2,3,4
1,2,3,4
1,2,3,4
1,2,3,4
1,2,3,4
1,2,3,4
t
DQSCK
t
CH
t
CL
t
CK
t
CK
CL=2.5
CL=2
Clock cycle time
t
DH
DQ and DM input hold time
0.5
0.5
0.6
ns
1,2,3,4
,15,16
t
DS
DQ and DM input setup time
0.5
0.5
0.6
ns
1,2,3,4
,15,16
t
DIPW
DQ and DM input pulse width (each input)
1.75
1.75
2
ns
1,2,3,4
t
HZ
Data-out high-impedance time from
CK/
CK
-0.75
+0.75
-0.75
+0.75
-0.8
+0.8
ns
1, 2, 3,
4, 5
t
LZ
Data-out low-impedance time from
CK/
CK
-0.75
+0.75
-0.75
+0.75
-0.8
+0.8
ns
1, 2, 3,
4, 5
t
DQSQ
DQS-DQ skew (DQS & associated DQ
signals)
DQS-DQ skew (DQS & all DQ signals)
Minimum half clk period for any given
cycle; defined by clk high(t
CH
)
or clk low (t
CL
) time
0.5
0.5
0.6
ns
1,2,3,4
t
DQSQA
0.5
0.5
0.6
ns
1,2,3,4
t
HP
t
CH
or
t
CL
t
HP
-
0.75ns
t
CH
or
t
CL
t
HP
-
0.75ns
t
CH
or
t
CL
t
HP
-
1.0ns
t
CK
1,2,3,4
t
QH
Data output hold time from DQS
t
CK
1,2,3,4
t
DQSS
Write command to 1st DQS latching
transition
DQS input low (high) pulse width
(write cycle)
DQS falling edge to CK setup time
(write cycle)
DQS falling edge hold time from CK
(write cycle)
Mode register set command cycle time
0.75
1.25
0.75
1.25
0.75
1.25
t
CK
1,2,3,4
t
DQSL,H
0.35
0.35
0.35
t
CK
1,2,3,4
t
DSS
0.2
0.2
0.2
t
CK
1,2,3,4
t
DSH
0.2
0.2
0.2
t
CK
1,2,3,4
t
MRD
14
15
16
ns
1,2,3,4
t
WPRES
Write preamble setup time
0
0
0
ns
1, 2, 3,
4, 7
t
WPST
Write postamble
0.40
0.60
0.40
0.60
0.40
0.60
t
CK
1, 2, 3,
4, 6
1,2,3,4
2, 3, 4,
9, 11,
12
2, 3, 4,
9, 11,
12
2, 3, 4,
10, 11,
12,
14
t
WPRE
Write preamble
0.25
0.25
0.25
t
CK
t
IH
Address and control input hold time
(fast slew rate)
0.9
1.1
1.1
ns
t
IS
Address and control input setup time
(fast slew rate)
0.9
1.1
1.1
ns
t
IH
Address and control input hold time
(slow slew rate)
1.0
1.1
1.1
ns
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PDF描述 |
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| NT256D64S88A0G-75B | 184pin One Bank Unbuffered DDR SDRAM MODULE |
| NT256D64S88A0G-7K | 184pin One Bank Unbuffered DDR SDRAM MODULE |
| NT256D64S88A0G-8B | 184pin One Bank Unbuffered DDR SDRAM MODULE |
| NT256D64S88A2GM | 200pin One Bank Unbuffered DDR SO-DIMM |
| NT256D64S88A2GM-75B | 200pin One Bank Unbuffered DDR SO-DIMM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NT256D64S88A0G-75B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:184pin One Bank Unbuffered DDR SDRAM MODULE |
| NT256D64S88A0G-7K | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:184pin One Bank Unbuffered DDR SDRAM MODULE |
| NT256D64S88A0G-8B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:184pin One Bank Unbuffered DDR SDRAM MODULE |
| NT256D64S88A2GM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:200pin One Bank Unbuffered DDR SO-DIMM |
| NT256D64S88A2GM-75B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:200pin One Bank Unbuffered DDR SO-DIMM |
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