參數(shù)資料
型號: NT128D64S88A0G
廠商: Electronic Theatre Controls, Inc.
英文描述: 184pin One Bank Unbuffered DDR SDRAM MODULE
中文描述: 一位銀行無緩沖184pin DDR SDRAM內(nèi)存模塊
文件頁數(shù): 1/15頁
文件大?。?/td> 191K
代理商: NT128D64S88A0G
NT128D64S88A0G
128MB : 16M x 64
PC2100 / PC1600 Unbuffered DIMM
184pin One Bank
Unbuffered DDR SDRAM MODULE
Based on DDR266/200 16Mx8 SDRAM
Features
184-Pin Unbuffered 8-Byte Dual In-Line Memory Module
16Mx64 Double Data Rate (DDR) SDRAMDIMM
(16M X 8 SDRAMS)
Performance :
PC1600
PC2100
Speed Sort
- 8B
- 75B
- 7K
DIMM
CAS
Latency
2
2.5
2
f
CK
Clock Frequency
100
133
133
MHz
t
CK
Clock Cycle
10
7.5
7.5
ns
f
DQ
DQ Burst Frequency
200
266
266
MHz
Intended for 100 MHz and 133 MHz applications
Inputs and outputs are SSTL-2 compatible
V
DD
= 2.5Volt ±
0.2, V
DD
= 2.5Volt ± 0.2
Single Pulsed
RAS
interface
SDRAMs have 4 internal banks for concurrent operation
Module has one physical bank
Differential clock inputs
Description
NT128D64S88A0G is an unbuffered 184-Pin Double Data Rate (DDR) Synchronous DRAM Dual In-Line Memory Module (DIMM),
REV1.0
/
June 2001
1
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Unit
Data is read or written on both clock edges
DRAM D
LL
aligns DQ and DQS transitions with clock transitions.
Also aligns QFC transitions with clock during Read cycles
Address and control signals are fully synchronous to positive
clock edge
Programmable Operation:
- DIMM
CAS
Latency: 2, 2.5
- Burst Type: Sequential or Interleave
- Burst Length: 2, 4, 8
- Operation: Burst Read and Write
Auto Refresh (CBR) and Self Refresh Modes
Automatic and controlled precharge commands
12/10/2 Addressing (row/column/bank)
15.6 μs Max. Average Periodic Refresh Interval
Serial Presence Detect
Gold contacts
SDRAMs in 66-pin TSOP Type II Package
organized as a one-bank high-speed memory array. The 16Mx64 module is a single-bank DIMM that uses eight 16Mx8 DDR
SDRAMs in 400 mil TSOP packages. The DIMM achieves high-speed data transfer rates of up to 266MHz. The DIMM is intended for use
in applications operating from 100 MHz to 133 MHz clock speeds with data rates of 200 to 266 MHz. Clock enable CKE0 controls all
devices on the DIMM.
Prior to any access operation, the device
CAS
latency and burst type/ length/operation type must be programmed into the DIMM by
address inputs A0-A11 and I/O inputs BA0 and BA1 using the mode register set cycle.
These DIMMs are manufactured using raw cards developed for broad industry use as reference designs. The use of these common
design files minimizes electrical variation between suppliers.
The DIMM uses serial presence detects implemented via a serial EEPROM using the two-pin IIC protocol. The first 128 bytes of serial PD
data are programmed and locked during module assembly. The last 128 bytes are available to the customer.
All NANYA 184 DDR SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a 5.25” long space-saving footprint.
Ordering Information
Part Number
Speed
Organization
Leads
Power
143MHz (7ns @ CL = 2.5 )
NT128D64S88A0G-7K
133MHz (7.5ns @ CL= 2 )
PC2100
133MHz (7.5ns @ CL= 2.5 )
NT128D64S88A0G –75B
100MHz (10ns @ CL = 2 )
PC2100
125MHz (8ns @ CL = 2.5 )
NT128D64S88A0G –8B
100MHz (10ns @ CL = 2 )
PC1600
16Mx64
Gold
2.5V
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