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參數(shù)資料
| 型號(hào)： | NS486SXLVUL |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Optimized 32-Bit 486-Class Controller with On-Chip Peripherals for Embedded Systems |
| 中文描述： | 優(yōu)化的32位486級(jí)控制器的片上外圍設(shè)備的嵌入式系統(tǒng) |
| 文件頁數(shù)： | 2/6頁 |
| 文件大?。?/td> | 466K |
| 代理商： | NS486SXLVUL |
Table of Contents
1.0 System Overview
1.1 NS486SXL System Overview
1.2 32-bit Processor Core
1.3 System Service Elements
1.3.1 DRAM Controller
1.3.2 Programmable Interval Timer
1.3.3 WATCHDOG Timer
1.3.4 Interrupt Controller
1.3.5 Real Time Clock/Calendar
1.3.6 Power Management Features
1.4 NS486SXL System Bus
1.5 Other On-board Peripherals
1.5.1 Reconfigurable I/O Lines
1.5.2 MICROWIRE/Access.bus Interface
1.5.3 UART Serial Port
1.6 ICE Support
1.7 Other Issues
2.0 SXL Pin Description Tables
3.0 Device Specifications
3.1 DC Electrical Specifications 5V
±
5%
3.1.1 Recommended Operating Conditions
3.1.2 Absolute Maximum Ratings (Notes 2 and 3)
3.1.3 Capacitance: T
A
= 25C, f = 1 MHz
3.1.4 DC Characteristics
3.2 General AC Specifications
3.2.1 Power Ramp Times
3.2.2 PWRGOOD and Power Rampdown Timing
3.3 AC Switching Specifications
3.3.1 DRAM Interface Timing Specification
3.3.2 ISA-like Bus Cycles Timing Specification
3.3.3 Ready Feedback Timing Specifications
3.3.4 OSCX1 AC Specification
4.0 NS486SXL Physical Description
List of Tables
Table 1. Bus Interface Unit Pins
Table 2. External Bus Master Interface Pins
Table 3. DRAM Control Pins
Table 4. Power Pins
Table 5. Reset Logic Pins
Table 6. General Purpose Chip Select Pins
Table 7. Auxiliary Processor Interface Pins
Table 8. Test Pins
Table 9. Interrupt Control Pins
Table 10. Real Time Clock Pins
Table 11. Oscillator Pins
Table 12. 16550 UART Pins
Table 13. Timer Pins
Table 14. 3-Wire Serial I/O Pins
List of Figures
FIGURE 1. NS486SXL Internal Resource to Pins Map
FIGURE 2.NS486SXL Internal Busses
FIGURE 3. NS486SXL Package Pinout Diagram
FIGURE 4. Switching Characteristic Measurement Wave-
forms
FIGURE 5. More Switching Specifications
FIGURE 6. Power Supply Rise and Fall
FIGURE 7. PWGOOD in relation to V
DD
FIGURE 8. DRAM Timing Diagram
FIGURE 9. ISA-like Bus Timing Diagram
FIGURE 10. Ready Feedback Timing Diagram
FIGURE 11.TTL Clock Input Timing Diagram
FIGURE 12. PIC Timing Diagram
FIGURE 13. Access.bus Timing Diagram
FIGURE 14. UART Baud Rate and Infrared Clocks
FIGURE 16. UART MODEM Control Timing
FIGURE 17. NS486SXL Package
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