參數(shù)資料
型號(hào)： NS32FX164V-20
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 數(shù)字信號(hào)處理
英文描述： Advanced Imaging/Communication Signal Processors
中文描述： 16-BIT, 40 MHz, MIXED DSP, PQCC68
封裝： PLASTIC, LCC-68
文件頁(yè)數(shù)： 68/102頁(yè)
文件大?。?/td> 1053K
代理商： NS32FX164V-20
3.0 Functional Description
(Continued)
TABLE 3-6. Data Access Sequences
Cycle
Type
Address
HBE
A0
High Bus
Low Bus
A. Odd Word Access Sequence
Byte 1
Byte 0
w
A
1
2
Odd Byte
Even Byte
A
A
a
1
0
1
1
0
Byte 0
Don’t Care
Don’t Care
Byte 1
B. Even Double-Word Access Sequence
Byte 3
Byte 2
Byte 1
Byte 0
w
A
1
1
Even Word
Even Word
A
A
a
2
0
0
0
0
Byte 1
Byte 3
Byte 0
Byte 2
C. Odd Double-Word Access Sequence
Byte 3
Byte 2
Byte 1
Byte 0
w
A
1
2
3
Odd Byte
Even Word
Even Byte
A
A
a
1
A
a
3
0
0
1
1
0
0
Byte 0
Byte 2
Don’t Care
Don’t Care
Byte 1
Byte 3
D. Even Quad-Word Access Sequence
Byte 7
Byte 6
Byte 5
Byte 4
Byte 3
Byte 2
Byte 1
Byte 0
w
A
1
2
Even Word
Even Word
A
A
a
2
0
0
0
0
Byte 1
Byte 3
Byte 0
Byte 2
Other Bus Cycles (Instruction Prefetch or Slave) can occur here.
3
4
Even Word
Even Word
A
a
4
A
a
6
0
0
0
0
Byte 5
Byte 7
Byte 4
Byte 6
E. Odd Quad-Word Access Sequence
Byte 7
Byte 6
Byte 5
Byte 4
Byte 3
Byte 2
Byte 1
Byte 0
w
A
1
2
3
Odd Byte
Even Word
Even Byte
A
A
a
1
A
a
3
0
0
1
1
0
0
Byte 0
Byte 2
Don’t Care
Don’t Care
Byte 1
Byte 3
Other Bus Cycles (Instruction Prefetch or Slave) can occur here.
4
5
6
Odd Byte
Even Word
Even Byte
A
a
4
A
a
5
A
a
7
0
0
1
1
0
0
Byte 4
Byte 6
Don’t Care
Don’t Care
Byte 5
Byte 7
3.5.5.9 Bus Access Control
The NS32FX164 CPU has the capability of relinquishing its
control of the bus upon request from a DMA controller or
another CPU. This capability is implemented by means of
the HOLD (Hold Request) and HLDA (Hold Acknowledge)
pins. By asserting HOLD low, an external device requests
access to the bus. On receipt of HLDA from the CPU, the
device may perform bus cycles, as the CPU at this point has
set AD0–AD15, A16–A23 and HBE to the TRI-STATE
é
condition and has switched ADS and DDIN to the input
mode. ALE is asserted in T4, and stays high during the time
the bus is granted. The CPU now monitors ADS and DDIN
from the external device to generate the relevant strobe
signals (i.e., TSO, DBE, RD or WR). To return control of the
bus to the CPU, the device sets HOLD inactive, and the
CPU acknowledges it by setting HLDA inactive.
68
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