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| 型號(hào)： | NS32FX164-20 |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | Advanced Imaging/Communication Signal Processors(高級(jí)圖象/通訊信號(hào)處理器) |
| 中文描述： | 16-BIT, 40 MHz, MIXED DSP, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 8/102頁 |
| 文件大小： | 1053K |
| 代理商： | NS32FX164-20 |
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2.0 Architectural Description
(Continued)
2.1.2 Address Registers
The seven address registers are used by the processor to
implement specific address functions. Except for the MOD
register that is 16 bits wide, all the others are 32 bits. A
description of the address registers follows.
PCDProgram Counter.
The PC register is a pointer to the
first byte of the instruction currently being executed. The PC
is used to reference memory in the program section.
SP0, SP1DStack Pointers.
The SP0 register points to the
lowest address of the last item stored on the INTERRUPT
STACK. This stack is normally used only by the operating
system. It is used primarily for storing temporary data, and
holding return information for operating system subroutines
and interrupt and trap service routines. The SP1 register
points to the lowest address of the last item stored on the
USER STACK. This stack is used by normal user programs
to hold temporary data and subroutine return information.
When a reference is made to the selected Stack Pointer
(see PSR S-bit), the terms ‘‘SP Register’’ or ‘‘SP’’ are used.
SP refers to either SP0 or SP1, depending on the setting of
the S bit in the PSR register. If the S bit in the PSR is 0, SP
refers to SP0. If the S bit in the PSR is 1 then SP refers to
SP1.
Stacks in the Series 32000 architecture grow downward in
memory. A Push operation pre-decrements the Stack Point-
er by the operand length. A Pop operation post-increments
the Stack Pointer by the operand length.
FPDFrame Pointer.
The FP register is used by a procedure
to access parameters and local variables on the stack. The
FP register is set up on procedure entry with the ENTER
instruction and restored on procedure termination with the
EXIT instruction.
The frame pointer holds the address in memory occupied by
the old contents of the frame pointer.
SBDStatic Base.
The SB register points to the global vari-
ables of a software module. This register is used to support
relocatable global variables for software modules. The SB
register holds the lowest address in memory occupied by
the global variables of a module.
INTBASEDInterrupt Base.
The INTBASE register holds
the address of the dispatch table for interrupts and traps
(Section 3.2.1).
MODDModule.
The MOD register holds the address of the
module descriptor of the currently executing software mod-
ule. The MOD register is 16 bits long, therefore the module
table must be contained within the first 64 kbytes of memo-
ry.
2.1.3 Processor Status Register
The Processor Status Register (PSR) holds status informa-
tion for the microprocessor.
The PSR is sixteen bits long, divided into two eight-bit
halves. The low order eight bits are accessible to all pro-
grams, but the high order eight bits are accessible only to
programs executing in Supervisor Mode.
15
8
7
0
B
I
P
S
U
N
Z
F
J
K
L
T
C
FIGURE 2-2. Processor Status Register (PSR)
C
The C bit indicates that a carry or borrow occurred after
an addition or subtraction instruction. It can be used with
the ADDC and SUBC instructions to perform multiple-
precision integer arithmetic calculations. It may have a
setting of 0 (no carry or borrow) or 1 (carry or borrow).
T
The T bit causes program tracing. If this bit is set to 1, a
TRC trap is executed after every instruction (Section
3.3.1).
L
The L bit is altered by comparison instructions. In a com-
parison instruction the L bit is set to ‘‘1’’ if the second
operand is less than the first operand, when both oper-
ands are interpreted as unsigned integers. Otherwise, it
is set to ‘‘0’’. In Floating-Point comparisons, this bit is
always cleared.
K
Reserved for use by the CPU.
J
Reserved for use by the CPU.
F
The F bit is a general condition flag, which is altered by
many instructions (e.g., integer arithmetic instructions
use it to indicate overflow).
Z
The Z bit is altered by comparison instructions. In a com-
parison instruction the Z bit is set to ‘‘1’’ if the second
operand is equal to the first operand; otherwise it is set
to ‘‘0’’.
N
The N bit is altered by comparison instructions. In a
comparison instruction the N bit is set to ‘‘1’’ if the sec-
ond operand is less than the first operand, when both
operands are interpreted as signed integers. Otherwise,
it is set to ‘‘0’’.
U
If the U bit is ‘‘1’’ no privileged instructions may be exe-
cuted. If the U bit is ‘‘0’’ then all instructions may be
executed. When U
e
0 the processor is said to be in Su-
pervisor Mode; when U
e
1 the processor is said to be in
User Mode. A User Mode program is restricted from exe-
cuting certain instructions and accessing certain regis-
ters which could interfere with the operating system. For
example, a User Mode program is prevented from
changing the setting of the flag used to indicate its own
privilege mode. A Supervisor Mode program is assumed
to be a trusted part of the operating system, hence it has
no such restrictions.
S
The S bit specifies whether the SP0 register or SP1 reg-
ister is used as the Stack Pointer. The bit is automatical-
ly cleared on interrupts and traps. It may have a setting
of 0 (use the SP0 register) or 1 (use the SP1 register).
P
The P bit prevents a TRC trap from occurring more than
once for an instruction (Section 3.3.1). It may have a
setting of 0 (no trace pending) or 1 (trace pending).
If I
e
1, then all interrupts will be accepted. If I
e
0, only
fected by this bit.
I
8
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PDF描述 |
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| NS32FV16-25 | Advanced Imaging/Communication Signal Processors |
| NS32FX164-25 | Advanced Imaging/Communication Signal Processors(高級(jí)圖象/通訊信號(hào)處理器) |
| NS32FX161-15 | Advanced Imaging/Communication Signal Processors(高級(jí)圖象/通訊信號(hào)處理器) |
| NS32FX161-20 | Advanced Imaging/Communication Signal Processors(高級(jí)圖象/通訊信號(hào)處理器) |
| NS32FX164V-15 | Advanced Imaging/Communication Signal Processors |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NS32FX164-25 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Advanced Imaging/Communication Signal Processors |
| NS32FX164AV-25 | 功能描述:IC IMAGING COMM SGNL PROC PLCC68 RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:- 標(biāo)準(zhǔn)包裝:2 系列:MPC8xx 處理器類型:32-位 MPC8xx PowerQUICC 特點(diǎn):- 速度:133MHz 電壓:3.3V 安裝類型:表面貼裝 封裝/外殼:357-BBGA 供應(yīng)商設(shè)備封裝:357-PBGA（25x25） 包裝:托盤 |
| NS32FX164V-15 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Advanced Imaging/Communication Signal Processors |
| NS32FX164V-20 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Advanced Imaging/Communication Signal Processors |
| NS32FX164V-25 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Advanced Imaging/Communication Signal Processors |
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