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參數(shù)資料
| 型號： | NS32FX161-20 |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Advanced Imaging/Communication Signal Processors(高級圖象/通訊信號處理器) |
| 中文描述： | 16-BIT, 40 MHz, MIXED DSP, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 37/102頁 |
| 文件大?。?/td> | 1053K |
| 代理商： | NS32FX161-20 |
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3.0 Functional Description
(Continued)
3.2.4 Non-Maskable Interrupt
The Non-Maskable Interrupt is triggered whenever a falling
edge is detected on the NMI pin. The CPU performs an
‘‘Interrupt Acknowledge’’ bus cycle from Address FFFF00
16
when processing of this interrupt actually begins. The vector
value used for the Non-Maskable Interrupt is taken as 1,
regardless of the value read from the bus.
The service procedure returns from the Non-Maskable-In-
terrupt using the Return from Trap (RETT) instruction. No
special bus cycles occur on return.
3.2.5 Traps
Traps are processing exceptions that are generated as di-
rect results of the execution of an instruction.
The return address saved on the stack by any trap except
Trap (TRC) is the address of the first byte of the instruction
during which the trap occurred.
When a trap is recognized, maskable interrupts are not dis-
abled.
There are 8 trap conditions recognized by the NS32FX164
as described below.
Trap (SLAVE):
An exceptional condition was detected by
the Floating-Point Unit during the execution of a Slave In-
struction. This trap is requested via the Status Word re-
turned as part of the Slave Processor Protocol (Section
3.1.3.1).
Trap (ILL):
Illegal operation. A privileged operation was at-
tempted while the CPU was in User Mode (PSR bit U
e
1).
Trap (SVC):
The Supervisor Call (SVC) instruction was exe-
cuted.
Trap (DVZ):
An attempt was made to divide an integer by
zero. (The FPU trap is used for Floating-Point division by
zero.)
Trap (FLG):
The FLAG instruction detected a ‘‘1’’ in the
PSR F-bit.
Trap (BPT):
The Breakpoint (BPT) instruction was execut-
ed.
Trap (TRC):
The instruction just completed is being traced.
Refer to Section 3.3.1 for details.
Trap (UND):
An undefined opcode was encountered by the
CPU.
3.2.6 Priority among Exceptions
The CPU checks for specific exceptions at various points
while executing an instruction. It is possible that several ex-
ceptions occur simultaneously. In that event, the CPU re-
sponds to the exception with highest priority.
Figure 3-11 shows an exception processing flowchart.
Before executing an instruction, the CPU checks for pend-
ing interrupts, or Trap (TRC). The CPU responds to any
pending interrupt requests; nonmaskable interrupts are rec-
ognized with higher priority than maskable interrupts. If no
interrupts are pending, then the CPU checks the P-flag in
the PSR to determine whether a Trap (TRC) is pending. If
the P-flag is 1, a Trap (TRC) is processed. If no interrupt or
Trap (TRC) is pending, the CPU begins executing the in-
struction.
While executing an instruction, the CPU may recognize up
to two exceptions:
1. Interrupt, if the instruction is interruptible.
2. One of 7 mutually exclusive traps: SLAVE, ILL, SVC,
DVZ, FLG, BPT, UND
If no exception is detected while the instruction is executing,
then the instruction is completed and the PC is updated to
point to the next instruction.
37
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| NS32FX164V-15 | Advanced Imaging/Communication Signal Processors |
| NS32FX164V-20 | Advanced Imaging/Communication Signal Processors |
| NS32FX164V-25 | Advanced Imaging/Communication Signal Processors |
| NS32FX200-20 | System Controller(系統(tǒng)控制器) |
| NS32FV100FV | System Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NS32FX16-15 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Imaging/Signal Processor |
| NS32FX16-20 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Imaging/Signal Processor |
| NS32FX16-25 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Imaging/Signal Processor |
| NS32FX164 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| NS32FX164-20 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Advanced Imaging/Communication Signal Processors |
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