參數(shù)資料
型號(hào): NS32FV100FV
廠商: National Semiconductor Corporation
英文描述: System Controller
中文描述: 系統(tǒng)控制器
文件頁(yè)數(shù): 56/94頁(yè)
文件大?。?/td> 955K
代理商: NS32FV100FV
3.0 System Interface
(Continued)
TL/EE/11331–39
FIGURE 3-7. Zone 2 (DRAM) Refresh Transaction, Zero Wait State
TL/EE/11331–40
*
If a new CPU/DMA transaction to either Zone 0, 1 or 2 is started during the refresh transaction, it is postponed by CWAIT until the refresh is completed and for at
least two more cycles (postponed T1, T2).
FIGURE 3-8. Zone 2 (DRAM) Refresh Transaction, Three Wait States
Figure 3-9 shows the Freeze Mode refresh transaction waveforms with RCFG.RFRT
e
5.
TL/EE/11331–41
FIGURE 3-9. Freeze Mode Refresh Transaction Waveform
56
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