參數(shù)資料
型號(hào): NS32FV100-25
廠商: National Semiconductor Corporation
英文描述: System Controller(系統(tǒng)控制器)
中文描述: 系統(tǒng)控制器(系統(tǒng)控制器)
文件頁(yè)數(shù): 74/94頁(yè)
文件大小: 955K
代理商: NS32FV100-25
4.0 Device Specifications
(Continued)
4.6.2 Timing Tables
(Continued)
4.6.2.1 Output Signals: Internal Propagation Delays
(Continued)
Symbol
Figure
Description
Reference/
Condition
NS32FX200-15
NS32FX200-20
NS32FX200-25
Units
Min
Max
Min
Max
Min
Max
t
SMPHa
4-23
SMPH0–3 Signal
Active
After R.E.,
CTTL
24
22
20
ns
t
SMPHia
4-23
SMPH0–3 Signal
Inactive
After R.E.,
CTTL
24
22
20
ns
t
STBa
4-21
STB0–3 Signal
Active
After R.E.,
CTTL
t
CTp2
t
CTp2
a
24
t
CTp2
t
CTp2
a
22
t
CTp2
t
CTp2
a
20
ns
t
STBia
4-21
STB0–3 Signal
Inactive
After R.E.,
CTTL
t
CTp/2
t
CTp/2
a
24
t
CTp/2
t
CTp/2
a
22
t
CTp/2
t
CTp/2
a
20
ns
t
PMPHa
4-21
PMPH0-3 Signal
Active
After R.E.,
CTTL
24
22
20
ns
t
PMPHia
4-21
PMPH0–3 Signal
Inactive
After R.E.,
CTTL
24
22
20
ns
t
BUZCLKa
4-26
BUZCLK Signal
Active
After R.E.,
CTTL
t
CTp/2
t
CTp/2
a
24
t
CTp/2
t
CTp/2
a
22
t
CTp/2
t
CTp/2
a
20
ns
t
BUZCLKia
4-26
BUZCLK Signal
Inactive
After R.E.,
CTTL
t
CTp/2
t
CTp/2
a
24
t
CTp/2
t
CTp/2
a
22
t
CTp/2
t
CTp/2
a
20
ns
t
WDTa
4-22
WDT Signal
Active
After R.E.,
CTTL
24
22
20
ns
t
INTRa
4-18
INTR Signal
Active
After R.E.,
CTTL
t
CTp/2
t
CTp/2
a
24
t
CTp/2
t
CTp/2
a
22
t
CTp/2
t
CTp/2
a
20
ns
t
INTRia
4-18
INTR Signal
Inactive
After R.E.,
CTTL
t
CTp/2
t
CTp/2
a
24
t
CTp/2
t
CTp/2
a
22
t
CTp/2
t
CTp/2
a
20
ns
t
MWSKa
4-25
MWSK Signal
Active
After R.E.,
CTTL
t
CTp/2
t
CTp/2
a
24
t
CTp/2
t
CTp/2
a
22
t
CTp/2
t
CTp/2
a
20
ns
t
MWSKia
4-25
MWSK Signal
Active
After R.E.,
CTTL
t
CTp/2
t
CTp/2
a
24
t
CTp/2
t
CTp/2
a
22
t
CTp/2
t
CTp/2
a
20
ns
t
DMAKa
4-16
DMAK0–3 Signal
Active
After R.E.,
CTTL
24
22
20
ns
t
DMAKia
4-16
DMAK0–3 Signal
Inactive
After R.E.,
CTTL
24
22
20
ns
t
PEXTa
4-26
PEXT Signal
Active
After R.E.,
CTTL
24
22
22
ns
t
PEXTia
4-26
PEXT Signal
Inactive
After R.E.,
CTTL
24
22
22
ns
t
PDOEv
4-21
PDO Signal Valid,
(External Clock Mode)
After F.E., PCLK
Input
33
33
33
ns
t
PDOIv
4-21
PDO Signal Valid,
(Internal Clock Mode)
After R.E., CTTL
(Note 1)
26
24
22
ns
t
PCLKa
4-21
PCLK Signal
Active
After R.E.,
CTTL
t
CTp/2
t
CTp/2
a
24
t
CTp/2
t
CTp/2
a
22
t
CTp/2
t
CTp/2
a
20
ns
t
PCLKia
4-21
PCLK Signal
Inactive
After R.E.,
CTTL
t
CTp/2
t
CTp/2
a
24
t
CTp/2
t
CTp/2
a
22
t
CTp/2
t
CTp/2
a
20
ns
Note 1:
PDO is changed on the first CTTL R.E. following the PCLK F.E.
74
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