參數(shù)資料
型號: NS16C2552TVA
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 微控制器/微處理器
英文描述: Dual UART with 16-byte/64-byte FIFOs and up to 5 Mbit/s Data Rate
中文描述: 2 CHANNEL(S), 5M bps, SERIAL COMM CONTROLLER, PQCC44
封裝: PLASTIC, LCC-44
文件頁數(shù): 9/43頁
文件大?。?/td> 881K
代理商: NS16C2552TVA
6.0 Register Set
There are two identical register sets, one for each channel,
in the DUART.All register descriptions in this section apply to
the register sets in both channels.
To clarify the descriptions of transmission and receiving op-
erations, the nomenclatures through out this documentation
are as follows:
Frame - Refers to all the bits between Start and Stop.
Character or word - The payload of a frame, between 5 to
8 bits.
“!=” - Not equal to.
Res - Reserved bit.
The address and control pins to register selection is summa-
rized in
Table 1
.
TABLE 1. Basic Register Addresses
DLAB1
CHSL
A2
A1
A0
Register
C
H
A
N
N
E
L
1
0
1
0
0
0
Receive Buffer (Read), Transmitter Holding Register
(Write)
Interrupt Enable
Interrupt Identification (Read)
FIFO Control (Write)
Line Control
Modem Control
Line Status (Read)
Modem Status (Read)
Scratchpad
Divisor Latch (Least Significant Byte)
Divisor Latch (Most Significant Byte)
Alternate Function
Register
Receive Buffer (Read), Transmitter Holding Register
(Write)
Interrupt Enable
Interrupt Identification (Read)
FIFO Control (Write)
Line Control
Modem Control
Line Status (Read)
Modem Status (Read)
Scratchpad
Divisor Latch (Least Significant Byte)
Divisor Latch (Most Significant Byte)
Alternate Function
0
0
0
x
x
x
x
x
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
C
H
A
N
N
E
L
2
DLAB1
0
CHSL
0
A2
0
A1
0
A0
0
0
0
0
x
x
x
x
x
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
N
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