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參數(shù)資料
| 型號： | NMC27C64QE |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | 65,536-BIT (8192 X 8) CMOS EPROM |
| 中文描述： | 65,536位（8192 × 8）的CMOS存儲器 |
| 文件頁數(shù)： | 4/10頁 |
| 文件大小： | 175K |
| 代理商： | NMC27C64QE |
4
www.fairchildsemi.com
NMC27C64 Rev. C
N
Capacitance
TA = +25
C, f = 1 MHz (Note 2) NMC27C64Q
Symbol
Parameter
Conditions
Typ
Max
Units
C
IN
Input Capacitance
V
IN
= 0V
6
8
pF
C
OUT
Output Capacitance
V
OUT
= 0V
9
12
pF
Capacitance
TA = +25
C, f = 1 MHz (Note 2) NMC27C64N
Symbol
Parameter
Conditions
Typ
Max
Units
C
IN
Input Capacitance
V
IN
= 0V
5
10
pF
C
OUT
Output Capacitance
V
OUT
= 0V
8
10
pF
AC Test Conditions
Output Load
1 TTL Gate and C
L
= 100 pF (Note 8)
Input Rise and Fall Times
5 ns
Input Pulse Levels
0.45V to 2.4V
Timing Measurement Reference Level
Inputs
Outputs
0.8V and 2V
0.8V and 2V
AC Waveforms
(Note 6) (Note 9)
Note 1:
Stresses above those listed under
“
Absolute Maximum Ratings
”
may cause permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Note 2:
This parameter is only sampled and is not 100% tested.
Note 3:
OE may be delayed up to t
ACC
- t
OE
after the falling edge of CE without impacting t
ACC
.
Note 4:
The t
and t
compare level is determined as follows:
High to TRI-STATE
, the measured V
(DC)
0.10V;
Low to TRI-STATE, the measured V
OL1
(DC) + 0.10V.
Note 5:
TRI-STATE may be attained using OE or CE .
Note 6:
The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1 F ceramic capacitor be used on every device
between V
CC
and GND.
Note 7:
The outputs must be restricted to V
CC
+ 1.0V to avoid latch-up and device damage.
Note 8:
1 TTL Gate: I
= 1.6 mA, I
= -400 A.
C
L
: 100 pF includes fixture capacitance.
Note 9:
V
PP
may be connected to V
CC
except during programming.
Note 10:
Inputs and outputs can undershoot to -2.0V for 20 ns Max.
Address Valid
Valid Output
Hi-Z
2V
0.8V
2V
0.8V
2V
0.8V
ADDRESS
OUTPUT
CE
OE
t
CE
2V
0.8V
(Note 3)
(Note 3)
t
DF
t
CF
(Notes 4, 5)
(Notes 4, 5)
t
OH
Hi-Z
t
OE
ACC
t
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